ZL38065
Pin Description (continued)
Pin #
Pin
Name
208-Ball LBGA
F0i
B5
100 Pin
LQFP
62
Description
Data Sheet
Frame Pulse (Input).
This input accepts and automatically
identifies frame synchronization signals formatted according to
ST-BUS or GCI interface specifications.
Serial Clock (Input).
4.096 MHz serial clock for shifting data
in/out on the serial streams (Rin, Sin, Rout, Sout).
Master Clock (Input).
Nominal 10 MHz or 20 MHz Master Clock
input. May be connected to an asynchronous (relative to frame
signal) clock source.
Frequency select (Input).
This input selects the Master Clock
frequency operation. When Fsel pin is low, nominal 19.2 MHz
Master Clock input must be applied. When Fsel pin is high,
nominal 9.6 MHz Master Clock input must be applied.
PLL Ground.
Must be connected to V
SS
PLL Power Supply.
Must be connected to V
DD2
= 1.8 V
Test Mode Select (3.3 V Input).
JTAG signal that controls the
state transitions of the TAP controller. This pin is pulled high by
an internal pull-up when not driven.
Test Serial Data In (3.3 V Input).
JTAG serial test instructions
and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
Test Serial Data Out (Output).
JTAG serial data is output on this
pin on the falling edge of TCK. This pin is held in high impedance
state when JTAG scan is not enabled.
Test Clock (3.3 V Input).
Provides the clock to the JTAG test
logic.
Test Reset (3.3 V Input).
Asynchronously initializes the JTAG
TAP controller by putting it in the Test-Logic-Reset state. This pin
should be pulsed low on power-up or held low, to ensure that the
ZL38065 is in the normal functional mode. This pin is pulled by
an internal pull-down when not driven.
Device Reset (Schmitt Trigger Input).
An active low resets the
device and puts the ZL38065 into a low-power stand-by mode.
When the RESET pin is returned to logic high and a clock is
applied to the MCLK pin, the device will automatically execute
initialization routines, which preset all the Main Control and
Status Registers to their default power-up values.
C4i
MCLK
A4
G2
63
90
Fsel
H2
92
PLLVss1
K3
PLLVss2
PLLV
DD
K4
TMS
M2
97, 95
96
1
TDI
M1
2
TDO
N1
3
TCK
TRST
P1
N2
4
6
RESET
R3
8
9
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
