ZL49010/11, ZL49020/21, ZL49030/31
Data Sheet
of four pulses will be ignored until the next rising edge of the ESt/DStD. ACK should idle at logic low. The 4-bit
binary representing all 16 standard DTMF digits are shown in Table 2.
Powerdown Mode (ZL4901x/4903x)
The ZL4901x/4903x devices offer a powerdown function to preserve power consumption when the device is not in
use. A logic high can be applied at the PWDN pin to place the device in powerdown mode. The ACK pin should be
kept at logic low to avoid undefined ESt/DStD and SD outputs (see Table 3).
F
LOW
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
F
HIGH
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
DIGIT
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
b
3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
b
2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
b
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
b
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0= LOGIC LOW, 1= LOGIC HIGH
Note: b0=LSB of decoded DTMF digit and shifted out first.
Table 2 - Serial Decode Bit Table
ACK (input)
low
low
high
high
Note:
+
PWDN (input)
low
high
+
low
high
ESt/DStD (output)
Refer to Fig. 4 for
timing waveforms
low
low
undefined
Table 3 - Powerdown Mode
SD (output)
Refer to Fig. 4 for
timing waveforms
low
undefined
undefined
ZL4901x/4903x
status
normal operation
powerdown mode
undefined
undefined
=enters powerdown mode on the rising edge.
5
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
