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ZL50234QCG1 参数 Datasheet PDF下载

ZL50234QCG1图片预览
型号: ZL50234QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 8信道语音回声消除器 [8 Channel Voice Echo Canceller]
分类和应用: 数字传输接口电信电路
文件页数/大小: 44 页 / 659 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50234
8 Channel Voice Echo Canceller
Data Sheet
Features
Independent multiple channels of echo
cancellation; from 8 channels of 64 ms to 4
channels of 128 ms with the ability to mix
channels at 128 ms or 64 ms in any combination
Independent Power Down mode for each group of
2 channels for power management
Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
Passed AT&T voice quality testing for carrier
grade echo cancellers.
Compatible to ST-BUS and GCI interfaces with
2 Mbps serial PCM data
PCM coding,
µ/A-Law
ITU-T G.711 or sign
magnitude
Per channel Fax/Modem G.164 2100 Hz or G.165
2100 Hz phase reversal Tone Disable
Per channel echo canceller parameters control
Transparent data transfer and mute
Fast reconvergence on echo path changes
Fully programmable convergence speeds
Patented Advanced Non-Linear Processor with
high quality subjective performance
Ordering Information
ZL50234/QCC
ZL50234/GDC
ZL50234QCG1
100 Pin LQFP Trays
208 Ball PBGA Trays
100 Pin LQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
March 2006
Protection against narrow band signal divergence
and instability in high echo environments
+9 dB to -12 dB level adjusters (3 dB steps) at all
signal ports
Offset nulling of all PCM channels
10 MHz or 20 MHz master clock operation
3.3 V I/O pads and 1.8 V Logic core operation with
5 V tolerant inputs
IEEE-1149.1 (JTAG) Test Access Port
ZL50232, ZL50233, ZL50234 and ZL50235 have
same pinouts in both LQFP and LBGA packages
Applications
Voice over IP network gateways
Voice over ATM, Frame Relay
T1/E1/J1 multichannel echo cancellation
V
DD1 (3.3 V)
V
SS
V
DD2 (1.8 V)
ODE
Rin
Sin
Serial
to
Parallel
Echo Canceller Pool
Group 0
ECA/ECB
Parallel
to
Serial
Rout
Sout
Fsel
MCLK
PLL
Group 1
ECA/ECB
Group 2
ECA/ECB
Group 3
ECA/ECB
Note:
Refer to Figure 4
for Echo Canceller
block diagram
C4i
F0i
Timing
Unit
RESET
Microprocessor Interface
Test Port
DS CS R/W A10-A0 DTA
D7-D0
IRQ TMS TDI TDO TCK TRST
Figure 1 - ZL50234 Device Overview
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.