Z8 Encore! XP® 4K Series
Product Specification
19
Table 8. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
PDOUT
—
Reset (Hex)
Page #
FDF
Port D Output Data
Reserved
00
42
FE0–FEF
XX
Watch-Dog Timer (WDT)
FF0
Reset Status (Read-only)
RSTSTAT
WDTCTL
WDTU
WDTH
WDTL
—
X0
N/A
00
27
86
87
87
88
Watch-Dog Timer Control (Write-only)
Watch-Dog Timer Reload Upper Byte
Watch-Dog Timer Reload High Byte
Watch-Dog Timer Reload Low Byte
Reserved
FF1
FF2
04
FF3
00
FF4–FF5
XX
Trim Bit Control
FF6
FF7
Trim Bit Address
Trim Bit Data
TRMADR
TRMDR
00
00
150
151
Flash Memory Controller
FF8
FF8
FF9
Flash Control
FCTL
FSTAT
FPS
00
00
00
00
00
00
144
145
146
146
147
147
Flash Status
Flash Page Select
Flash Sector Protect
FPROT
FFA
FFB
Flash Programming Frequency High Byte FFREQH
Flash Programming Frequency Low Byte FFREQL
eZ8 CPU
FFC
Flags
—
XX
XX
XX
XX
Refer to the
eZ8 CPU User
Manual
FFD
Register Pointer
Stack Pointer High Byte
Stack Pointer Low Byte
RP
FFE
SPH
SPL
FFF
XX=Undefined
PS022815-0206
Register Map
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