欢迎访问ic37.com |
会员登录 免费注册
发布采购

Z8F021APB020EC 参数 Datasheet PDF下载

Z8F021APB020EC图片预览
型号: Z8F021APB020EC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采! XP -R 4K系列高性能8位微控制器 [Z8 Encore! XP-R 4K Series High-Performance 8-Bit Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 276 页 / 3422 K
品牌: ZILOG [ ZILOG, INC. ]
 浏览型号Z8F021APB020EC的Datasheet PDF文件第41页浏览型号Z8F021APB020EC的Datasheet PDF文件第42页浏览型号Z8F021APB020EC的Datasheet PDF文件第43页浏览型号Z8F021APB020EC的Datasheet PDF文件第44页浏览型号Z8F021APB020EC的Datasheet PDF文件第46页浏览型号Z8F021APB020EC的Datasheet PDF文件第47页浏览型号Z8F021APB020EC的Datasheet PDF文件第48页浏览型号Z8F021APB020EC的Datasheet PDF文件第49页  
Z8 Encore! XP
®
4K Series
Product Specification
26
(RSTSTAT) Register is set to 1.
lists the STOP Mode Recovery sources and
resulting actions. The text following provides more detailed information about each of the
STOP Mode Recovery sources.
Table 11. STOP Mode Recovery Sources and Resulting Action
Operating Mode
STOP mode
STOP Mode Recovery Source
Watch-Dog Timer time-out
when configured for Reset
Watch-Dog Timer time-out
when configured for interrupt
Data transition on any GPIO Port pin
enabled as a STOP Mode Recovery
source
Assertion of external
RESET
Pin
Debug Pin driven Low
Action
STOP Mode Recovery
STOP Mode Recovery followed by
interrupt (if
interrupts are enabled)
STOP Mode Recovery
System Reset
System Reset
STOP Mode Recovery Using Watch-Dog Timer Time-Out
If the Watch-Dog Timer times out during STOP mode, the device undergoes a STOP
Mode Recovery sequence. In the Reset Status (RSTSTAT) register, the WDT and STOP
bits are set to 1. If the Watch-Dog Timer is configured to generate an interrupt upon time-
out and the Z8 Encore! XP
®
4K Series device is configured to respond to interrupts, the
eZ8 CPU services the Watch-Dog Timer interrupt request following the normal STOP
Mode Recovery sequence.
STOP Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO Port pins may be configured as a STOP Mode Recovery input source.
On any GPIO pin enabled as a STOP Mode Recovery source, a change in the input pin
value (from High to Low or from Low to High) initiates STOP Mode Recovery. Note that
SMR pulses shorter than specified will not trigger a recovery. (See
When this happens, the
STOP
bit in the Reset Status (RSTSTAT) register is set
to 1.
Caution:
In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the Port transition only if the signal stays on the Port pin through
the end of the STOP Mode Recovery delay. As a result, short pulses on the Port pin can
initiate STOP Mode Recovery without being written to the Port Input Data register or
without initiating an interrupt (if enabled for that pin).
PS022815-0206
Reset, STOP Mode Recovery and Low Voltage Detection