341MIC贸易商引脚图技术参数全新原装-中国IC网-芯三七

DATASHEET

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

ICS341

Description

Features

The ICS341 is a low cost, single-output, field programmable

clock synthesizer. The ICS341 can generate an output

frequency from 250 kHz to 200 MHz and may employ

Spread Spectrum techniques to reduce system

electro-magnetic interference (EMI).

• 8-pin SOIC package

• Highly accurate frequency generation

•M/N Multiplier PLL: M = 1...2048, N = 1...1024

• Output clock frequencies up to 200 MHz

• Four ROM locations for frequency and spread selection

• Spread spectrum capability for lower system EMI

•Center or Down Spread up to 4% total

™

Using IDT’s VersaClock software to configure the PLL and

output, the ICS341 contains a One-Time Programmable

(OTP) ROM to allow field programmability. Programming

features include 4 selectable configuration registers.

•Selectable 32 kHz or 120 kHz modulation

The device employs Phase-Locked Loop (PLL) techniques

to run from a standard fundamental mode, inexpensive

crystal, or clock. It can replace multiple crystals and

oscillators, saving board space and cost.

• Input crystal frequency from 5 to 27 MHz

• Input clock frequency from 2 to 50 MHz

• Operating voltage of 3.3 V

• Advanced, low-power CMOS process

• For two output clocks, use the ICS342. For three output

clocks, see the ICS343. For more than three outputs, see

the ICS345 or ICS348.

The device also has a power-down feature that tri-states the

clock outputs and turns off the PLLs when the PDTS pin is

taken low.

• Available in Pb (lead) free packaging

NOTE: EOL for non-green parts to occur on 5/13/10

per PDN U-09-01

The ICS341 is also available in factory programmed custom

versions for high-volume applications.

Block Diagram

VDD

OTP ROM

with PLL

Divider

2

S1:0

Values

PLL Clock Synthesis,

Spred Spectrum and

Control Circuitry

CLK

Crystal or

clock input

X1/ICLK

Crystal

Oscillator

X2

GND

External capacitors are

required with a crystal input.

PDTS (output and PLL)

IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

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Pin Assignment

Output Clock Selection Table

S1

S0

CLK (MHz)

Spread

Percentage

User

Configurable

User

X1/ I CLK

VDD

8

7

6

5

1

2

3

4

X2

0

User

Configurable

User

Configurable

User

PDTS

S1

GND

S0

0

1

Configurable

User

CLK

1

0

Configurable

User

Configurable

User

Configurable

1

8-pin (150 mil) SOIC

Pin Descriptions

Number

Name

Type

Pin Description

1

2

3

4

5

6

X1/ICLK

VDD

GND

S0

XI

Connect this pin to a crystal or external clock input.

Connect to +3.3 V.

Power

Input

Connect to ground.

Select pin 0 for frequency selection on CLK. Internal pull-up resistor.

CLK

S1

Output Clock output. Weak internal pull-down when tri-state.

Input

XO

Select pin 1 for frequency selection on CLK. Internal pull-up resistor.

Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up

resistor.

7

8

PDTS

X2

Connect this pin to a crystal, or float for clock input.

External Components

capacitance. Because load capacitance can only be

increased in this trimming process, it is important to keep

stray capacitance to a minimum by using very short PCB

traces (and no vias) between the crystal and device. Crystal

capacitors must be connected from each of the pins X1 and

X2 to ground.

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50Ω trace (a commonly

used trace impedance), place a 33Ω resistor in series with

the clock line, as close to the clock output pin as possible.

The nominal impedance of the clock output is 20Ω.

The value (in pF) of these crystal caps should equal (C -6

L

Decoupling Capacitor

pF)*2. In this equation, C = crystal load capacitance in pF.

L

As with any high-performance mixed-signal IC, the ICS341

must be isolated from system power supply noise to perform

optimally.

Example: For a crystal with a 16 pF load capacitance, each

crystal capacitor would be 20 pF [(16-6) x 2] = 20.

PCB Layout Recommendations

A decoupling capacitor of 0.01µF must be connected

between VDD and the PCB ground plane.

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

Crystal Load Capacitors

1) The 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible. No vias should be used between the decoupling

capacitor and VDD pin. The PCB trace to VDD pin should be

The device crystal connections should include pads for

small capacitors from X1 to ground and from X2 to ground.

These capacitors are used to adjust the stray capacitance of

the board to match the nominally required crystal load

IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

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kept as short as possible, as should the PCB trace to the

ground via. Distance of the ferrite bead and bulk decoupling

from the device is less critical.

VersaClock software quickly evaluates accessible VCO

frequencies with available output divide values and provides

an easy to understand, bar code rating for the target output

frequencies. The user may evaluate output accuracy,

performance trade-off scenarios in seconds.

2) The external crystal should be mounted just next to the

device with short traces. The X1 and X2 traces should not

be routed next to each other with minimum spaces, instead

they should be separated and away from other traces.

Spread Spectrum Modulation

The ICS341 utilizes frequency modulation (FM) to distribute

energy over a range of frequencies. By modulating the

output clock frequencies, the device effectively lowers

energy across a broader range of frequencies; thus,

lowering a system’s electro-magnetic interference (EMI).

The modulation rate is the time from transitioning from a

minimum frequency to a maximum frequency and then back

to the minimum.

3) To minimize EMI, the 33Ω series termination resistor (if

needed) should be placed close to the clock output.

4) An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers. Other signal traces should be routed away from the

ICS341. This includes signal traces just underneath the

device, or on layers adjacent to the ground plane layer used

by the device.

Spread Spectrum Modulation can be applied as either

“center spread” or “down spread”. During center spread

modulation, the deviation from the target frequency is equal

in the positive and negative directions. The effective average

frequency is equal to the target frequency. In applications

where the clock is driving a component with a maximum

frequency rating, down spread should be applied. In this

case, the maximum frequency, including modulation, is the

target frequency. The effective average frequency is less

than the target frequency.

ICS341 Configuration Capabilities

The architecture of the ICS341 allows the user to easily

configure the device to a wide range of output frequencies,

for a given input reference frequency.

The frequency multiplier PLL provides a high degree of

precision. The M/N values (the multiplier/divide values

available to generate the target VCO frequency) can be set

within the range of M = 1 to 2048 and N = 1 to 1024.

The ICS341 operates in both center spread and down

spread modes. For center spread, the frequency can be

modulated between +/- 0.125% to +/-2.0%. For down

spread, the frequency can be modulated between -0.25% to

-4.0%.

The ICS341 also provides separate output divide values,

from 2 through 20, to allow the two output clock banks to

support widely differing frequency values from the same

PLL.

Both output frequency banks will utilize identical spread

spectrum percentage deviations and modulation rates, if a

common VCO frequency can be identified.

Each output frequency can be represented

as:

Spread Spectrum Modulation Rate

REFFreq

OutputDivide

M

----

--------------------------------------

OutputFreq =

⋅

N

The spread spectrum modulation frequency applied to the

output clock frequency may occur at a variety of rates. For

applications requiring the driving of “down-circuit” PLLs,

Zero Delay Buffers, or those adhering to PCI standards, the

spread spectrum modulation rate should be set to 30-33

kHz. For other applications, a 120 kHz modulation option is

available.

IDT VersaClock Software

IDT applies years of PLL optimization experience into a user

friendly software that accepts the user’s target reference

clock and output frequencies and generates the lowest jitter,

lowest power configuration, with only a press of a button.

The user does not need to have prior PLL experience or

determine the optimal VCO frequency to support multiple

output frequencies.

IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

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Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS341. These ratings, which are

standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these

or any other conditions above those indicated in the operational sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical

parameters are guaranteed only over the recommended operating temperature range.

Parameter

Condition

Min.

-0.5

-65

Typ.

Max.

7

Units

V

Supply Voltage, VDD

Inputs

Referenced to GND

VDD+ 0.5

150

V

Clock Outputs

V

Storage Temperature

Soldering Temperature

Junction Temperature

°C

Max 10 seconds

260

125

Recommended Operation Conditions

Parameter

Min.

0

Typ.

Max.

+70

+85

+3.45

4

Units

° C

Ambient Operating Temperature (ICS341M)

Ambient Operating Temperature (ICS341MI)

Power Supply Voltage (measured in respect to GND)

Power Supply Ramp Time

-40

° C

+3.15

+3.3

V

ms

IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

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DC Electrical Characteristics

Unless stated otherwise, VDD = 3.3V ±±5, Ambient Temperature -40 to +85°C

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

V

Operating Voltage

VDD

3.15

3.3

3.45

Configuration Dependent

- See VersaClock

mA

TM

33.3333 MHz output,

PDTS = 1, no load

Note 1

11

20

mA

Operating Supply Current

Input High Voltage

IDD

PDTS = 0

S1:S0

µA

V

Input High Voltage

V

2

IH

Input Low Voltage

V

S1:S0

0.4

V

IL

Input High Voltage, PDTS

Input Low Voltage, PDTS

Input High Voltage

V

VDD-0.5

VDD/2+1

IH

V

IL

V

ICLK

IH

Input Low Voltage

V

VDD/2-1

IL

Output High Voltage

(CMOS High)

V

I

= -4 mA

VDD-0.4

2.4

OH

Output High Voltage

Output Low Voltage

Short Circuit Current

V

I

= -12 mA

= 12 mA

V

OH

V

0.4

OL

I

70

20

mA

Ω

OS

Nominal Output

Impedance

Z

O

Internal pull-up resistor

Internal pull-down resistor

Input Capacitance

R

S1:S0

250

525

4

kΩ

pF

PUP

PDTS

R

CLK output

inputs

PD

C

IN

Note 1: Example with 25 MHz crystal input with output of 33.3 MHz, no load, and VDD = 3.3 V.

IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

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AC Electrical Characteristics

Unless stated otherwise, VDD = 3.3V ±±5, Ambient Temperature -40 to +85° C

Parameter

Symbol

Conditions

Fundamental Crystal

Input Clock

Min.

5

Typ. Max. Units

Input Frequency

F

27

50

MHz

ns

IN

2

Output Frequency

Output Rise Time

Output Fall Time

Duty Cycle

0.25

200

t

20% to 80%, Note 1

80% to 20%, Note 1

Note 2

1

OR

t

ns

OF

40

49-51

TBD

60

%

Output Frequency Synthesis

Error

Configuration Dependent

ppm

Power-up Time

PLL lock time from

power-up

4

10

2

ms

PDTS goes high until

stable CLK output,

Spread Spectrum Off

.2

PDTS goes high until

stable CLK output,

Spread Spectrum On

4

7

ms

One Sigma Clock Period Jitter

Maximum Absolute Jitter

Configuration Dependent

50

ps

t

Deviation from Mean.

+200

ja

Configuration Dependent

Note 1: Measured with 15 pF load.

Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.

Note 3: ICS test mode output occurs for first 170 clock cycles on CLK for each PLL powered up. PDTS transition

high on select address change.

Thermal Characteristics

Parameter

Symbol

Conditions

Min.

Typ. Max. Units

Thermal Resistance Junction to

Ambient

θ

Still air

150

140

120

40

° C/W

JA

θ

1 m/s air flow

3 m/s air flow

JA

θ

JA

Thermal Resistance Junction to Case

θ

JC

IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

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Package Outline and Package Dimensions (8-pin SOIC, 1±0 Mil. Body)

Package dimensions are kept current with JEDEC Publication No. 95

8

Millimeters

Inches

Symbol

Min

1.35

0.10

0.33

0.19

4.80

3.80

Max

1.75

0.25

0.51

0.25

5.00

4.00

Min

Max

A

A1

B

C

D

E

e

.0532

.0040

.013

.0688

.0098

.020

E

H

INDEX

AREA

.0075

.1890

.1497

.0098

.1968

.1574

1.27 BASIC

0.050 BASIC

1

2

H

h

5.80

0.25

0.40

0°

6.20

0.50

1.27

8°

.2284

.010

.016

0°

.2440

.020

.050

8°

D

L

α

A

h x 45

A1

C

- C -

e

SEATING

PLANE

B

L

.10 (.004)

C

IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

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Ordering Information

Part / Order Number

341MP*

Marking

341MP

341MIP

341MPLF

341MIPLF

341M-XX

341MI-XX

341MXXLF

341MIXXL

Shipping Packaging

Tubes

Package

8-pin SOIC

Temperature

0 to +70° C

-40 to +85° C

0 to +70° C

-40 to +85° C

0 to +70° C

-40 to +85° C

0 to +70° C

-40 to +85° C

341MPT*

341MIP*

341MIPT*

341MPLF

Tape and Reel

Tubes

Tape and Reel

Tubes

Tape and Reel

Tubes

Tape and Reel

Tubes

Tape and Reel

Tubes

Tape and Reel

Tubes

Tape and Reel

Tubes

Tape and Reel

341MPLFT

341MIPLF

341MIPLFT

341M-XX*

341M-XXT*

341MI-XX*

341MI-XXT*

341M-XXLF

341M-XXLFT

341MI-XXLF

341MI-XXLFT

*NOTE: EOL for non-green parts to occur on ±/13/10 per PDN U-09-01

Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

The 341M-XX, 341M-XXLF, 341MI-XX, and 341MI-XXLF are factory programmed versions of the 341MP, 341MPLF, 341MIP, and

341MIPLF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept on

file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing

representative.

While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use

or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses

are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended

temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing

by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product

for use in life support devices or critical medical instruments.

IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

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EPROM CLOCK SYNTHESIZER

Innovate with IDT and accelerate your future networks. Contact:

www.IDT.com

For Sales

800-345-7015

408-284-8200

Fax: 408-284-2775

For Tech Support

www.idt.com/go/clockhelp

Corporate Headquarters

Integrated Device Technology, Inc.

www.idt.com

Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered

trademarks used to identify products or services of their respective owners.

Printed in USA

型号:	341M-XX
生命周期：	Obsolete
零件包装代码：	SOIC
包装说明：	0.150 INCH, SOIC-8
针数：	8
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.71
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0
长度：	4.9 mm
端子数量：	8
最高工作温度：	70 °C
最低工作温度：
最大输出时钟频率：	200 MHz
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
主时钟/晶体标称频率：	50 MHz
认证状态：	Not Qualified
座面最大高度：	1.75 mm
最大供电电压：	3.45 V
最小供电电压：	3.15 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	TIN LEAD
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
宽度：	3.9 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

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