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74HC4040; 74HCT4040

12-stage binary ripple counter

Rev. 03 — 14 September 2005

Product data sheet

1. General description

The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin

compatible with the HEF4040B series. They are speciﬁed in compliance with JEDEC

standard no. 7A.

The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP),

an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to

Q11). The counter advances on the HIGH-to-LOW transition of CP.

A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the

state of CP.

Each counter stage is a static toggle ﬂip-ﬂop.

2. Features

■ Multiple package options

■ Complies with JEDEC standard no. 7A

■ ESD protection:

◆ HBM JESD22-A114-C exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

■ Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Applications

■ Frequency dividing circuits

■ Time delay circuits

■ Control counters

4. Quick reference data

Table 1:

Quick reference data

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns.

Symbol Parameter

Type 74HC4040

t_PHL, t_PLHpropagation delay

Conditions

Min Typ Max Unit

CP to Q0

C_L= 15 pF; V_CC= 5 V

-

14

8

-

ns

Qn to Qn+1

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

Table 1:

Quick reference data …continued

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns.

Symbol

Parameter

Conditions

Min Typ Max Unit

f_max

maximum operating

frequency

C_L= 15 pF; V_CC= 5 V

-

90

-

MHz

C_i

input capacitance

-

3.5

20

-

pF

C_PD

power dissipation

capacitance

V_I= GND to V_CC

Type 74HCT4040

t_PHL, t_PLHpropagation delay

CP to Q0

C_L= 15 pF; V_CC= 5 V

-

16

8

-

ns

Qn to Qn+1

ns

f_max

maximum operating

frequency

79

MHz

C_i

input capacitance

-

3.5

20

-

pF

C_PD

power dissipation

capacitance

V_I= GND to V_CC− 1.5 V

[1] C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

∑(C_L× V_CC²× f_o) = sum of outputs;

C_L= output load capacitance in pF;

V_CC= supply voltage in V.

5. Ordering information

Table 2:

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74HC4040N

74HC4040D

74HC4040DB

−40 °C to +125 °C

DIP16

plastic dual in-line package; 16 leads (300 mil);

long body

SOT38-1

−40 °C to +125 °C

SO16

plastic small outline package; 16 leads; body

width 3.9 mm

SOT109-1

SSOP16

TSSOP16

plastic shrink small outline package; 16 leads; body SOT338-1

width 5.3 mm

74HC4040PW −40 °C to +125 °C

plastic thin shrink small outline package; 16 leads; SOT403-1

body width 4.4 mm

74HC4040BQ

−40 °C to +125 °C

DHVQFN16 plastic dual in-line compatible thermal enhanced

very thin quad ﬂat package; no leads; 16 terminals;

body 2.5 × 3.5 × 0.85 mm

SOT763-1

74HCT4040N

74HCT4040D

−40 °C to +125 °C

DIP16

plastic dual in-line package; 16 leads (300 mil);

long body

SOT38-1

SO16

plastic small outline package; 16 leads; body

width 3.9 mm

SOT109-1

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

2 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

Table 2:

Ordering information …continued

Type number

Package

Temperature range

Name

Description

Version

74HCT4040DB −40 °C to +125 °C

74HCT4040PW −40 °C to +125 °C

74HCT4040BQ −40 °C to +125 °C

SSOP16

plastic shrink small outline package; 16 leads; body SOT338-1

width 5.3 mm

TSSOP16

plastic thin shrink small outline package; 16 leads; SOT403-1

body width 4.4 mm

DHVQFN16 plastic dual in-line compatible thermal enhanced

very thin quad ﬂat package; no leads; 16 terminals;

body 2.5 × 3.5 × 0.85 mm

SOT763-1

6. Functional diagram

10

CP

T

12-STAGE COUNTER

11

MR

C

D

9

7

6

5

3

2

4

13 12 14 15

1

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11

001aad589

Fig 1. Functional diagram

CTR12

0

Q0

Q1

Q2

Q3

Q4

Q5

9

7

6

5

3

2

4

9

7

6

5

3

2

4

+

10

11

CT = 0

10

11

CP

CT

Q6

Q7

Q8

Q9

Q10

Q11

13

12

14

15

1

13

12

14

15

1

MR

11

001aad585

001aad586

Fig 2. Logic symbol

Fig 3. IEC logic symbol

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

3 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

Q

FF

1

FF

2

FF

3

FF

4

FF

5

FF

6

T

CP

RD

MR

Q0

Q1

Q2

Q3

Q4

Q5

Q

FF

7

FF

8

FF

9

FF

10

FF

11

FF

12

T

RD

Q6

Q7

Q8

Q9

Q10

Q11

001aad588

Fig 4. Logic diagram

7. Pinning information

7.1 Pinning

terminal 1

index area

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Q11

Q5

V

CC

2

3

4

5

6

7

15

14

13

12

11

10

Q5

Q10

Q9

Q10

Q9

Q7

Q8

MR

CP

Q0

Q4

Q6

Q3

Q2

Q1

Q4

Q7

Q6

4040

Q8

Q3

Q2

MR

CP

(1)

GND

Q1

GND

001aad583

001aad584

Transparent top view

(1) The substrate is attached to this pad

using conductive die attach material. It

can not be used as supply pin or input

Fig 5. Pin conﬁguration DIP16, SO16,

SSOP16 and TSSOP16

Fig 6. Pin conﬁguration DHVQFN16

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

4 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

7.2 Pin description

Table 3:

Symbol

Q11

Q5

Pin description

1

Description

output 11

output 5

2

Q4

3

output 4

Q6

4

output 6

Q3

5

output 3

Q2

6

output 2

Q1

7

output 1

GND

Q0

8

ground (0 V)

output 0

9

CP

10

11

12

13

14

15

16

clock input (HIGH-to-LOW, edge-triggered)

MR

master reset input (active HIGH)

output 8

Q8

Q7

output 7

Q9

output 9

Q10

V_CC

output 10

positive supply voltage

8. Functional description

8.1 Function table

Table 4:

Function table

Input

Output

CP

↑

MR

L

Q0 to Q11

no change

↓

L

count

L

X

H

[1] H = HIGH voltage level;

L = LOW voltage level;

X = don’t care;

↑ = LOW-to-HIGH clock transition;

↓ = HIGH-to-LOW clock transition.

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

5 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

8.2 Timing diagram

1

2

4

8

16

32

64 128 256 512 1024 2048 4096

CP input

MR input

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

001aad587

Fig 7. Timing diagram

9. Limiting values

Table 5:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+7

Unit

V

supply voltage

−0.5

input diode current

output diode current

output source or sink current

quiescent supply current

ground current

V_I< −0.5 V or VI > V_CC+ 0.5 V

V_I< −0.5 V or V_I> V_CC+ 0.5 V

−0.5 V < V_O< V_CC+ 0.5 V

-

±20

±25

±50

+150

mA

°C

I_OK

-

I_O

-

I_CC

-

I_GND

T_stg

P_tot

-

storage temperature

power dissipation

DIP16 package

−65

[1]

T_amb= −40 °C to +125 °C

-

750

500

mW

SO16, SSOP16, TSSOP16 and

DHVQFN16 packages

[1] For DIP16 packages: above 70 °C, P_totderates linearly with 12 mW/K.

For SO16, SSOP16, TSSOP16 and DHVQFN16 packages, above 70 °C, P_totderates linearly with 8 mW/K.

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

6 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

10. Recommended operating conditions

Table 6:

Symbol

Recommended operating conditions

Parameter

Conditions

Min

Typ

Max

Unit

type 74HC4040

V_CC

V_I

supply voltage

2.0

0

5.0

6.0

V

input voltage

-

V_CC

V_O

output voltage

0

T_amb

t_r, t_f

ambient temperature

input rise and fall times

see Section 11 and 12 per device

except for Schmitt-trigger inputs

V_CC= 2.0 V

−40

+125 °C

-

1000 ns

V_CC= 4.5 V

6.0

-

500

400

ns

V_CC= 6.0 V

type 74HCT4040

V_CC

V_I

supply voltage

4.5

0

5.0

5.5

V

input voltage

-

V_CC

V_O

output voltage

0

T_amb

t_r, t_f

ambient temperature

input rise and fall times

see Section 11 and 12 per device

except for Schmitt-trigger inputs

V_CC= 2.0 V

−40

+125 °C

-

ns

V_CC= 4.5 V

6.0

-

500

-

V_CC= 6.0 V

11. Static characteristics

Table 7:

Static characteristics for 74HC4040

Voltages are referenced to GND (ground = 0 V).

Symbol

T_amb= 25 °C

V_IH

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level input voltage

V_CC= 2.0 V

1.5

1.2

2.4

3.2

0.8

2.1

2.8

-

V

V_CC= 4.5 V

3.15

-

V_CC= 6.0 V

4.2

-

V_IL

LOW-level input voltage

HIGH-level output voltage

V_CC= 2.0 V

-

0.5

1.35

1.8

V_CC= 4.5 V

V_CC= 6.0 V

V_OH

V_I= V_IHor V_IL

I_O= −20 µA; V_CC= 2.0 V

I_O= −20 µA; V_CC= 4.5 V

I_O= −20 µA; V_CC= 6.0 V

I_O= −4.0 mA; V_CC= 4.5 V

I_O= −5.2 mA; V_CC= 6.0 V

1.9

2.0

-

V

4.4

4.5

5.9

6.0

3.98

5.48

4.32

5.81

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

7 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

Table 7:

Static characteristics for 74HC4040 …continued

Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_OL

LOW-level output voltage

V_I= V_IHor V_IL

I_O= 20 µA; V_CC= 2.0 V

I_O= 20 µA; V_CC= 4.5 V

I_O= 20 µA; V_CC= 6.0 V

I_O= 4.0 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

V_I= V_CCor GND; V_CC= 6.0 V

V_I= V_CCor GND; I_O= 0 A;

-

0

0.1

V

0

0.1

V

0

0.1

V

0.15

0.26

0.1

V

0.16

V

I_Ll

input leakage current

-

µA

I_CC

quiescent supply current

8.0

V_CC= 6.0 V

C_I

input capacitance

-

3.5

-

pF

T_amb= −40 °C to +85 °C

V_IHHIGH-level input voltage

V_CC= 2.0 V

1.5

-

V

V_CC= 4.5 V

3.15

-

V_CC= 6.0 V

4.2

-

V_IL

LOW-level input voltage

HIGH-level output voltage

V_CC= 2.0 V

-

0.5

1.35

1.8

V_CC= 4.5 V

V_CC= 6.0 V

V_OH

V_I= V_IHor V_IL

I_O= −20 µA; V_CC= 2.0 V

I_O= −20 µA; V_CC= 4.5 V

I_O= −20 µA; V_CC= 6.0 V

I_O= −4.0 mA; V_CC= 4.5 V

I_O= −5.2 mA; V_CC= 6.0 V;

V_I= V_IHor V_IL

1.9

-

V

4.4

5.9

3.84

5.34

V_OL

LOW-level output voltage

I_O= 20 µA; V_CC= 2.0 V

I_O= 20 µA; V_CC= 4.5 V

I_O= 20 µA; V_CC= 6.0 V

I_O= 4.0 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

V_I= V_CCor GND; V_CC= 6.0 V

V_I= V_CCor GND; I_O= 0 A;

V_CC= 6.0 V

-

0.1

V

0.1

V

0.1

V

0.33

1.0

V

I_Ll

input leakage current

µA

I_CC

quiescent supply current

80.0

T

_amb= −40 °C to +125 °C

V_IH

HIGH-level input voltage

LOW-level input voltage

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

1.5

-

V

3.15

-

4.2

-

V_IL

-

0.5

1.35

1.8

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

8 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

Table 7:

Static characteristics for 74HC4040 …continued

Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_OH

HIGH-level output voltage

V_I= V_IHor V_IL

I_O= −20 µA; V_CC= 2.0 V

I_O= −20 µA; V_CC= 4.5 V

I_O= −20 µA; V_CC= 6.0 V

I_O= −4.0 mA; V_CC= 4.5 V

I_O= −5.2 mA; V_CC= 6.0 V;

V_I= V_IHor V_IL

1.9

4.4

5.9

3.7

5.2

-

V

V_OL

LOW-level output voltage

I_O= 20 µA; V_CC= 2.0 V

I_O= 20 µA; V_CC= 4.5 V

I_O= 20 µA; V_CC= 6.0 V

I_O= 4.0 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

V_I= V_CCor GND; V_CC= 6.0 V

V_I= V_CCor GND; I_O= 0 A;

-

0.1

V

0.1

V

0.1

V

0.4

V

0.4

V

I_Ll

input leakage current

1.0

µA

I_CC

quiescent supply current

160.0

V_CC= 6.0 V

Table 8:

Static characteristics for 74HCT4040

Voltages are referenced to GND (ground = 0 V).

Symbol

T_amb= 25 °C

V_IH

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

V_CC= 4.5 V to 5.5 V

2.0

-

1.6

1.2

-

V

V_IL

V_CC= 4.5 V to 5.5 V

0.8

V_OH

V_I= V_IHor V_IL

I_O= −20 µA; V_CC= 4.5 V

I_O= −4.0 mA; V_CC= 4.5 V

V_I= V_IHor V_IL

4.4

4.5

-

V

3.98

4.32

V_OL

LOW-level output voltage

I_O= 20 µA; V_CC= 4.5 V

I_O= 4.0 mA; V_CC= 4.5 V

V_I= V_CCor GND; V_CC= 5.5 V

V_I= V_CCor GND; I_O= 0 A;

-

0

0.1

0.26

0.1

V

0.15

V

I_Ll

input leakage current

-

µA

I_CC

quiescent supply current

8.0

V_CC= 5.5 V

∆I_CC

additional quiescent supply V_I= V_CC− 2.1 V; V_CC= 4.5 V

current

to 5.5 V; I_O= 0 A

CP

-

85

306

396

-

µA

pF

MR

110

3.5

C_I

input capacitance

T_amb= −40 °C to +85 °C

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

V_CC= 4.5 V to 5.5 V

2.0

-

V

0.8

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

9 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

Table 8:

Static characteristics for 74HCT4040 …continued

Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_OH

HIGH-level output voltage

V_I= V_IHor V_IL

I_O= −20 µA; V_CC= 4.5 V

I_O= −4.0 mA; V_CC= 4.5 V

V_I= V_IHor V_IL

4.4

-

V

3.84

V_OL

LOW-level output voltage

I_O= 20 µA; V_CC= 4.5 V

I_O= 4.0 mA; V_CC= 4.5 V

V_I= V_CCor GND; V_CC= 5.5 V

V_I= V_CCor GND; I_O= 0 A;

-

0.1

V

0.33

1.0

V

I_Ll

input leakage current

µA

I_CC

quiescent supply current

80.0

V_CC= 5.5 V

∆I_CC

additional quiescent supply V_I= V_CC− 2.1 V; V_CC= 4.5 V

current

to 5.5 V; I_O= 0 A

CP

-

383

495

µA

MR

T_amb= −40 °C to +125 °C

V_IH

V_IL

HIGH-level input voltage

V_CC= 4.5 V to 5.5 V

2.0

-

V

LOW-level input voltage

HIGH-level output voltage

V_CC= 4.5 V to 5.5 V

0.8

V_OH

V_I= V_IHor V_IL

I_O= −20 µA; V_CC= 4.5 V

I_O= −4.0 mA; V_CC= 4.5 V

V_I= V_IHor V_IL

4.4

3.7

-

V

V_OL

LOW-level output voltage

I_O= 20 µA; V_CC= 4.5 V

I_O= 4.0 mA; V_CC= 4.5 V

V_I= V_CCor GND; V_CC= 5.5 V

V_I= V_CCor GND; I_O= 0 A;

-

0.1

V

0.4

V

I_Ll

input leakage current

1.0

µA

I_CC

quiescent supply current

160.0

V_CC= 5.5 V

∆I_CC

additional quiescent supply V_I= V_CC− 2.1 V; V_CC= 4.5 V

current

to 5.5 V; I_O= 0 A

CP

-

417

539

µA

MR

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

10 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

12. Dynamic characteristics

Table 9:

Dynamic characteristics for type 74HC4040

GND = 0 V; t_r= t_f= 6 ns. For test circuit see Figure 9.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_amb= 25 °C

t_PHL, t_PLH

propagation delay CP to Q0

see Figure 8

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

-

47

17

14

150

30

-

ns

26

propagation delay Qn to Qn+1

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

-

28

10

8

100

20

-

ns

8

17

t_PHL

propagation delay MR to Qn

output transition time

V_CC=2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

-

61

22

18

185

37

ns

31

t_THL, t_TLH

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

-

19

7

75

15

13

ns

6

t_W

clock pulse width HIGH or LOW

master reset pulse width; HIGH

recovery time MR to CP

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

80

16

14

5

-

ns

4

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

80

16

14

22

8

-

ns

6

t_rec

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

50

10

9

8

3

2

-

ns

f_max

maximum operating frequency

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V; C_L= 50 pF

6.0

30

-

27

82

90

98

20

-

MHz

pF

35

-

C_PD

power dissipation capacitance

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

11 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

Table 9:

Dynamic characteristics for type 74HC4040 …continued

GND = 0 V; t_r= t_f= 6 ns. For test circuit see Figure 9.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_amb= −40 °C to +85 °C

t_PHL, t_PLH

propagation delay CP to Q0

see Figure 8

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

-

190

38

ns

33

propagation delay Qn to Qn+1

propagation delay MR to Qn

output transition time

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

-

125

25

ns

21

t_PHL

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

-

230

46

ns

39

t_THL, t_TLH

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

-

95

19

16

ns

t_W

clock pulse width HIGH or LOW

master reset pulse width; HIGH

recovery time MR to CP

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

100

20

-

ns

17

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

100

20

-

ns

17

t_rec

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

65

13

11

-

ns

f_max

maximum operating frequency

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

4.8

24

28

-

MHz

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

12 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

Table 9:

Dynamic characteristics for type 74HC4040 …continued

GND = 0 V; t_r= t_f= 6 ns. For test circuit see Figure 9.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_amb= −40 °C to +125 °C

t_PHL, t_PLH

propagation delay CP to Q0

see Figure 8

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

-

225

45

ns

38

propagation delay Qn to Qn+1

propagation delay MR to Qn

output transition time

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

-

150

30

ns

26

t_PHL

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

-

280

56

ns

48

t_THL, t_TLH

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

-

110

22

ns

19

t_W

clock pulse width HIGH or LOW

master reset pulse width; HIGH

recovery time MR to CP

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

120

24

-

ns

20

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

120

24

-

ns

20

t_rec

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

see Figure 8

75

15

13

-

ns

f_max

maximum operating frequency

V_CC= 2.0 V; C_L= 50 pF

V_CC= 4.5 V; C_L= 50 pF

V_CC= 6.0 V; C_L= 50 pF

4.0

20

24

-

MHz

[1] C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

∑(C_L× V_CC²× f_o) = sum of outputs;

C_L= output load capacitance in pF;

V_CC= supply voltage in V.

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

13 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

Table 10: Dynamic characteristics for type 74HCT4040

GND = 0 V; t_r= t_f= 6 ns. For test circuit see Figure 9.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

T_amb= 25 °C

t_PHL, t_PLH

propagation delay CP to Q0

see Figure 8

V_CC= 4.5 V; C_L= 50 pF

V_CC= 5.0 V; C_L= 15 pF

see Figure 8

-

19

16

40

-

ns

propagation delay Qn to Qn+1

V_CC= 4.5 V; C_L= 50 pF

V_CC= 5.0 V; C_L= 15 pF

-

10

8

20

-

ns

t_PHL

propagation delay MR to Qn

output transition time

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

23

45

t_THL, t_TLH

t_W

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

-

7

6

2

15

-

ns

clock pulse width HIGH or LOW V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

16

10

master reset pulse width; HIGH

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

-

t_rec

recovery time MR to CP

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

-

f_max

maximum operating frequency

see Figure 8

V_CC= 4.5 V; C_L= 50 pF

V_CC= 5.0 V; C_L= 15 pF

30

-

72

79

20

-

MHz

pF

[1]

C_PD

power dissipation capacitance

per package

-

T_amb= −40 °C to +85 °C

t_PHL, t_PLH

propagation delay CP to Q0

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

-

50

25

56

19

-

ns

propagation delay Qn to Qn+1

propagation delay MR to Qn

output transition time

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

-

ns

t_PHL

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

-

ns

t_THL, t_TLH

t_W

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

-

ns

clock pulse width HIGH or LOW V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

20

13

24

ns

master reset pulse width; HIGH

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

-

ns

t_rec

recovery time MR to CP

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

-

ns

f_max

maximum operating frequency

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

-

MHz

T_amb= −40 °C to +125 °C

t_PHL, t_PLH

propagation delay CP to Q0

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8;

-

60

30

ns

propagation delay Qn to Qn+1

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

14 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

Table 10: Dynamic characteristics for type 74HCT4040 …continued

GND = 0 V; t_r= t_f= 6 ns. For test circuit see Figure 9.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_PHL

propagation delay MR to Qn

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8

-

68

ns

t_THL, t_TLH

t_W

output transition time

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8

-

22

-

ns

clock pulse width HIGH or LOW V_CC= 4.5 V; C_L= 50 pF;

see Figure 8

24

15

20

ns

master reset pulse width; HIGH

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8

-

ns

t_rec

recovery time MR to CP

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8

-

ns

f_max

maximum operating frequency

V_CC= 4.5 V; C_L= 50 pF;

see Figure 8

-

MHz

[1] C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

∑(C_L× V_CC²× f_o) = sum of outputs;

C_L= output load capacitance in pF;

V_CC= supply voltage in V.

13. Waveforms

V

I

V

MR input

CP input

M

t

1/f

W

max

t

rem

V

t

I

V

M

t

W

t

PHL

PLH

Q0 or Qn

output

V

M

t

TLH

THL

001aad590

74HC4040: V_M= 50 %; V_I= GND to V_CC

.

74HCT4040: V_M= 1.3 V; V_I= GND to 3 V.

Fig 8. Clock (CP) to output (Qn) propagation delays, clock pulse width, output transition

times, maximum clock pulse frequency, master reset (MR) pulse width, master

reset to output (Qn) propagation delays and master reset to clock (CP) removal

time.

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

15 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

V

CC

V

O

I

PULSE

GENERATOR

DUT

C

L

R

T

mna101

Deﬁnitions for test circuit:

C_L= load capacitance including jig and probe capacitance (See Section 12 for the value).

R_T= termination resistance should be equal to output impedance Z_Oof the pulse generator.

Fig 9. Test circuit

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

16 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

14. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil); long body

SOT38-1

D

M

E

A

2

A

1

L

c

e

w M

Z

b

1

(e )

1

b

16

9

M

H

pin 1 index

E

1

8

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

A

2

(1)

Z

1

w

UNIT

mm

b

c

D

E

e

L

M

H

1

E

max.

min.

max.

1.40

1.14

0.53

0.38

0.32

0.23

21.8

21.4

6.48

6.20

3.9

3.4

8.25

7.80

9.5

8.3

4.7

0.51

3.7

2.54

0.1

7.62

0.3

0.254

0.01

2.2

0.021

0.015

0.013

0.009

0.86

0.84

0.32

0.31

0.055

0.045

0.26

0.24

0.15

0.13

0.37

0.33

inches

0.19

0.02

0.15

0.087

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT38-1

050G09

MO-001

SC-503-16

Fig 10. Package outline SOT38-1 (DIP16)

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

17 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.39

0.014 0.0075 0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig 11. Package outline SOT109-1 (SO16)

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

18 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

8

1

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

p

1

2

3

E

max.

8^o

0^o

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2

7.9

7.6

1.03

0.63

0.9

0.7

1.00

0.55

mm

2

0.25

0.65

1.25

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT338-1

MO-150

Fig 12. Package outline SOT338-1 (SSOP16)

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

19 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 13. Package outline SOT403-1 (TSSOP16)

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

20 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

SOT763-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

7

L

1

8

9

E

h

e

16

15

10

D

h

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

3.6

3.4

2.15

1.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

2.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT763-1

- - -

MO-241

- - -

Fig 14. Package outline SOT763-1 (DHVQFN16)

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

21 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

15. Revision history

Table 11: Revision history

Document ID

Release date

Data sheet

status

Change

notice

Doc.

number

Supersedes

74HC_HCT4040_3

Modiﬁcations:

20050914

Product data

sheet

-

74HC_HCT4040_CNV_2

• The format of this data sheet has been redesigned to comply with the new presentation and

information standard of Philips Semiconductors

• Reference to family speciﬁcations is replaced by the actual information: Section 5 “Ordering

information”, Section 7 “Pinning information”, Section 9 “Limiting values”, Section 10

“Recommended operating conditions”, Section 11 “Static characteristics”, Figure 9 “Test

circuit”

• Section 14 “Package outline” (DHVQFN16) added

74HC_HCT4040_CNV_2 19901231

Product

-

speciﬁcation

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

22 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

16. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

17. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

19. Trademarks

Notice — All referenced brands, product names, service names and

18. Disclaimers

trademarks are the property of their respective owners.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

20. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

23 of 24

74HC4040; 74HCT4040

Philips Semiconductors

12-stage binary ripple counter

21. Contents

1

2

3

4

5

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8

8.1

8.2

Functional description . . . . . . . . . . . . . . . . . . . 5

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . 6

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Recommended operating conditions. . . . . . . . 7

Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

Dynamic characteristics . . . . . . . . . . . . . . . . . 11

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 23

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Contact information . . . . . . . . . . . . . . . . . . . . 23

10

11

12

13

14

15

16

17

18

19

20

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 14 September 2005

Document number: 74HC_HCT4040_3

Published in The Netherlands

型号:	74HCT4040D
是否Rohs认证：	符合
生命周期：	Active
包装说明：	SOP,
Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01
风险等级：	5.6
计数方向：	UP
系列：	HCT
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4
长度：	9.9 mm
负载/预设输入：	YES
逻辑集成电路类型：	BINARY COUNTER
工作模式：	ASYNCHRONOUS
湿度敏感等级：	1
位数：	12
功能数量：	1
端子数量：	16
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
传播延迟（tpd）：	60 ns
座面最大高度：	1.75 mm
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
触发器类型：	NEGATIVE EDGE
宽度：	3.9 mm
最小 fmax：	20 MHz
Base Number Matches：	1

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