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LVDS Dual-Frequency Programmable VCXO IDT8N4DV85

DATASHEET

General Description

Features

The IDT8N4DV85 is a LVDS Dual-Frequency Programmable VCXO

with very flexible frequency and pull-range programming capabilities.

The device uses IDT’s fourth generation FemtoClock® NG

technology for an optimum of high clock frequency and low phase

noise performance. The device accepts 2.5V or 3.3V supply and is

packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm

x 1.55mm package.

• Fourth generation FemtoClock® NG technology

• Programmable clock output frequency from 15.476MHz to

866.67MHz and from 975MHz to 1300MHz

• Two factory-programmed output frequencies

• Frequency programming resolution is 218Hz and better

• Absolute pull range (APR) programmable from 4.5 to 754.5ppm

• One 2.5V or 3.3V LVDS clock output

• Output enable control input, LVCMOS/LVTTL compatible

• RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.47ps (typical)

• 2.5V or 3.3V supply voltage

The device can be factory-programmed to any two frequencies in the

range of 15.476MHz to 866.67MHz and from 975MHz to 1300 MHz

to the very high degree of frequency precision of 218Hz or better.

The output frequency is selected by the FSEL pin. The extended

temperature range supports wireless infrastructure,

telecommunication and networking end equipment requirements.

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm

package

Block Diagram

Pin Assignment

PFD

&

LPF

FemtoClock® NG

VCO

1950-2600MHz

Q

nQ

÷P

OSC

114.285 MHz

÷N

VC 1

FSEL 2

GND 3

6 V

CC

5 nQ

4 Q

2

÷MINT, MFRAC

IDT8N4DV85

6-lead ceramic 5mm x 7mm x 1.55mm

package body

A/D

VC

9

7

23

Configuration Register (ROM)

(Frequency, Pull range, Polarity)

Pulldown

CD Package

Top View

FSEL

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Pin Description and Characteristic Tables

Table 1. Pin Descriptions

Number

Name

Type

Description

1

VC

Input

VCXO Control Voltage input.

Pulldown

Frequency select pin. See Table 3A for function. LVCMOS/LVTTL interface

levels.

2

FSEL

NOTE 1

3

4, 5

6

GND

Q, nQ

V_CC

Power

Output

Power

Negative power supply.

Differential clock output. LVDS interface levels.

Positive power supply.

NOTE 1.Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values

Table 2. Pin Characteristics

Symbol

Parameter

Test Conditions

Minimum

Typical

5.5

Maximum

Units

pF

FSEL

VC

Input

Capacitance

C_IN

10

pF

R_PULLDOWN

Input Pulldown Resistor

50

k

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Function Tables

NOTE 1

Table 3A. Output Frequency Range

15.476MHz to 866.67MHz

975MHz to 1300MHz

NOTE 1.Supported output frequency range. The output frequency

can be programmed to any frequency in this range and to a precision

of 218Hz or better.

Principles of Operation

The block diagram consists of the internal 3^RDovertone crystal and

oscillator which provide the reference clock f_XTALof 114.285MHz.

The PLL includes the FemtoClock NG VCO along with the

Pre-divider (P), the feedback divider (M) and the post divider (N). The

P, M, and N dividers determine the output frequency based on the

f_XTALreference. The feedback divider is fractional supporting a huge

number of output frequencies. Internal registers are used to hold up

to two different factory pre-set configuration settings. The

configuration is selected via the FSEL pin. Changing the FSEL

control results in an immediate change of the output frequency to the

selected register values. The P, M, and N frequency configurations

support an output frequency range 15.476MHz to 866.67MHz and

975MHz to 1,300MHz.

Table 3B. Frequency Selection

Input

FSEL

0 (default)

1

Selects

Frequency 0

Frequency 1

Frequency Configuration

An order code is assigned to each frequency configuration and the

VCXO pull-range programmed by the factory (default frequencies).

For more information on the available default frequencies and order

codes, please see the Ordering Information Section in this document.

For available order codes, see the FemtoClock NG Ceramic-Package

XO and VCXO Ordering Product Information document.

The devices use the fractional feedback divider with a delta-sigma

modulator for noise shaping and robust frequency synthesis

capability. The relatively high reference frequency minimizes phase

noise generated by frequency multiplication and allows more efficient

shaping of noise by the delta-sigma modulator. The output frequency

is determined by the 2-bit pre-divider (P), the feedback divider (M)

and the 7-bit post divider (N). The feedback divider (M) consists of

both a 7-bit integer portion (MINT) and an 18-bit fractional portion

(MFRAC) and provides the means for high-resolution frequency

generation. The output frequency f_OUTis calculated by:

For more information on programming capabilities of the device for

custom frequency and pull-range configurations, see the FemtoClock

NG Ceramic 5x7 Module Programming Guide.

1

P  N

MFRAC + 0.5

------------

-------------------------------------

f

= f



 MINT +

(1)

OUT

XTAL

18

2

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or

AC Characteristics is not implied. Exposure to absolute maximum rating conditions for 

extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_CC

Inputs, V_I

3.63V

-0.5V to V_CC+ 0.5V

Outputs, I_O(LVDS)

Continuous Current

Surge Current



10mA

15mA

Package Thermal Impedance, _JA

49.4C/W (0 mps)

-65C to 150C

Storage Temperature, T_STG

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, V = 3.3V 5%, T = -40°C to 85°C

CC

A

Symbol

V_CC

Parameter

Test Conditions

Minimum

Typical

3.3

Maximum

3.465

Units

V

Power Supply Voltage

Power Supply Current

3.135

I_DD

140

175

mA

Table 4B. Power Supply DC Characteristics, V = 2.5V 5%, T = -40°C to 85°C

CC

A

Symbol

V_CC

Parameter

Test Conditions

Minimum

Typical

3.3

Maximum

3.465

Units

V

Power Supply Voltage

Power Supply Current

3.135

I_DD

136

170

mA

Table 4C. LVCMOS/LVTTL DC Characteristic, V = 3.3V 5% or V = 2.5V 5%, T = -40°C to 85°C

CC

A

Symbol

Parameter

Test Conditions

V_CC= 3.3V

_CC= 2.5V

_CC= V_IN= 3.465V

_CC= V_IN= 2.5V

Minimum

Typical

Maximum

V_CC+ 0.3

0.8

Units

V

2

V_IH

Input High Voltage

V

1.7

-0.3

V

V_IL

Input Low Voltage

V

0.7

V

I_IH

I_IL

Input High Current

Input Low Current

FSEL

V_CC= V_IN= 3.465V or 2.625V

150

µA

V_CC= 3.465V or 2.625V, V_IN= 0V

-5

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LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Table 4D. LVDS DC Characteristics, V = 3.3V 5%, T = -40°C to 85°C

CC

A

Symbol

V_OD

Parameter

Test Conditions

Minimum

Typical

Maximum

454

Units

mV

V

Differential Output Voltage

V_ODMagnitude Change

Offset Voltage

247

330

V_OD

V_OS

50

1.14

1.23

1.31

50

V_OS

V_OSMagnitude Change

mV

Table 4E. LVDS DC Characteristics, V = 2.5V 5%, T = -40°C to 85°C

CC

A

Symbol

V_OD

Parameter

Test Conditions

Minimum

Typical

Maximum

454

Units

mV

V

Differential Output Voltage

V_ODMagnitude Change

Offset Voltage

247

320

V_OD

V_OS

50

1.13

1.22

1.30

50

V_OS

V_OSMagnitude Change

mV

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

AC Electrical Characteristics

Table 5A. AC Characteristics, V = 3.3V 5% or V = 2.5V 5%, T = -40°C to 85°C

CC

A

Symbol

f_OUT

f_I

Parameter

Test Conditions

Minimum

15.476

975

Typical

Maximum

Units

MHz

ppm

ps

866.67

1300

10

Output Frequency Q

Initial Accuracy

Measured @ 25°C, V_C= V_CC/2

Option code = A or B

100

50

f_S

f_A

f_T

Temperature Stability

Aging

Option code = E or F

Option code = K or L

20

Frequency drift over 10 year life

Frequency drift over 15 year life

Option code A, B (10 year life)

Option code E, F (10 year life)

Option code K, L (10 year life)

3

5

113

63

Total Stability

33

tjit(cc)

Cycle-to-Cycle Jitter^{NOTE 1}

RMS Period Jitter^NOTE1

6

4

14

tjit(per)

6

ps

RMS Phase Jitter

(Random)^{NOTE 2,3}

156.25MHz, Integration Range:

12kHz - 20MHz

tjit(Ø)

0.47

0.76

0.71

1.4

ps

15.576MHz  f_out 100MHz,

Integration Range:

12kHz - 20MHz

RMS Phase Jitter

(Random)^{NOTE 2,3}

f_XTAL= 114.285MHz

100MHz < f_out500MHz,

Integration Range:

12kHz - 20MHz

tjit(Ø)

0.48

0.46

0.63

0.67

ps

500MHz < f_out1300MHz,

Integration Range:

12kHz - 20MHz

Single-side band phase noise,

100Hz from Carrier

_N(100)

_N(1k)

156.25MHz

-58

-86

dBc/Hz

Single-side band phase noise, 

1kHz from Carrier

Single-side band phase noise, 

10kHz from Carrier

_N(10k)

_N(100k)

_N(1M)

_N(10M)

-111

-117

-126

-136

-58.7

Single-side band phase noise,

100kHz from Carrier

Single-side band phase noise, 

1MHz from Carrier

Single-side band phase noise, 

10MHz from Carrier

50mV Sinusoidal Noise

1kHz - 50MHz

PSNR

t_R/ t_F

Power Supply Noise Ratio

Output Rise/Fall Time

dBc/Hz

ps

20% to 80%

80

500

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Table 5A. AC Characteristics, V = 3.3V 5% or V = 2.5V 5%, T = -40°C to 85°C

CC

A

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

odc

Output Duty Cycle

45

55

%

Device startup time after

power-up

t_OSC

15

1

ms

Output frequency settling time

after FSEL0 and FSEL1 values

are changed

t_SET

NOTE 1.This parameter is defined in accordance with JEDEC standard 65.

NOTE 2. Refer to the phase noise plot.

NOTE 3. Refer to the FemtoClock NG Ceramic 5 x 7 Modules Programming Guide for additional information on PLL feedback modes and the

optimum configuration for phase noise.

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: Characterized with V_C= V_CC/2.

NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.

Table 5B. VCXO Control Voltage Input (V ) Characteristics, V = 3.3V 5% or V = 2.5V 5%, T = -40°C to 85°C

C

CC

A

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

477.27

630

Units

ppm/V

%

Oscillator Gain; NOTE 1, 2, 3

Oscillator Gain NOTE 1, 2, 3

Control Voltage Linearity

Modulation Bandwidth

VC Input Impedance

V_CC= 3.3V

V_CC= 2.5V

7.57

10

K_V

L_VC

BSL Variation

-1

0.1

100

+1

BW

kHz

k

Z_VC

500

VC_NOM

Nominal Control Voltage

V_CC/2

V

Control Voltage Tuning

Range; NOTE 4

V_C

0

V_CC

V

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1. V_C= 0V to V_CC.Oscillator gain is programmed by IDT. Gain = (25 * N) ÷ V_CCand is in the range of n = 1 to n = 63.

NOTE 2. Nominal oscillator gain: Refer to the programming guide for optimal pull range and control voltage tuning

NOTE 3. For best phase noise performance, use the lowest K_Vthat meets the requirements of the application.

NOTE 4. BSL = Best Straight Line Fit: Variation of the output frequency vs. control voltage V_Cin percent. V_Cranges from 10% to 90% V_CC

.

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

RMS Phase Jitter

Offset from Carrier Frequency (Hz)

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Parameter Measurement Information

SCOPE

Q

V

CC

3.3V 5%

POWER SUPPLY

2.5V 5%

POWER SUPPLY

+

Float GND –

+

Float GND –

nQ

3.3V LVDS Output Load AC Test Circuit

2.5V LVDS Output Load AC Test Circuit

nQ

Q

tcycle n

tcycle n+1

tjit(cc) = tcycle n – tcycle n+1

|

1000 Cycles

RMS Phase Jitter

Cycle-to-Cycle Jitter

V_OH

nQ

Q

V_REF

V_OL

1σ contains 68.26% of all measurements

2σ contains 95.4% of all measurements

3σ contains 99.73% of all measurements

4σ contains 99.99366% of all measurements

6σ contains (100-1.973x10^-7)% of all measurements

Histogram

Reference Point

(Trigger Edge)

Mean Period

(First edge after trigger)

RMS Period Jitter

Output Duty Cycle/Pulse Width/Period

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Parameter Measurement Information, continued

nQ

80%

t_F

80%

t_R

V_OD

20%

Q

Output Rise/Fall Time

Differential Output Voltage Setup

Offset Voltage Setup

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Applications Information

Recommendations for Unused Input Pins

Inputs:

LVCMOS Pins

All control pins have internal pulldowns; additional resistance is not

required but can be added for additional protection. A 1k resistor

can be used.

LVDS Driver Termination

For a general LVDS interface, the recommended value for the

termination impedance (Z_T) is between 90 and 132. The actual

value should be selected to match the differential impedance (Z₀) of

your transmission line. A typical point-to-point LVDS design uses a

100 parallel resistor at the receiver and a 100 differential

transmission-line environment. In order to avoid any

standard termination schematic as shown in Figure 1A can be used

with either type of output structure. Figure 1B, which can also be

used with both output types, is an optional termination with center tap

capacitance to help filter common mode noise. The capacitor value

should be approximately 50pF. If using a non-standard termination, it

is recommended to contact IDT and confirm if the output structure is

current source or voltage source type. In addition, since these

outputs are LVDS compatible, the input receiver’s amplitude and

common-mode input range should be verified for compatibility with

the output.

transmission-line reflection issues, the components should be

surface mounted and must be placed as close to the receiver as

possible. IDT offers a full line of LVDS compliant devices with two

types of output structures: current source and voltage source. The

Z_OZ_T

LVDS

Driver

LVDS

Receiver

Z_T

Figure 1A. Standard Termination

Z_T

Z_O Z_T

LVDS

Driver

2

Z_T

2

LVDS

Receiver

C

Figure 1B. Optional Termination

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Power Considerations

This section provides information on power dissipation and junction temperature for the IDT8N4DV85. 

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the IDT8N4DV85 is the sum of the core power plus the analog power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.3V + 5% = 3.465V, which gives worst case results.

•

Power (core)_MAX= V_{CC_MAX}* I_{CC_MAX}= 3.465V * 175mA = 606.375mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.606W * 49.4°C/W = 114.9°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 6. Thermal Resistance  for a 6-Lead Ceramic 5mm x 7mm Package, Forced Convection

JA

_JAvs. Air Flow

Meters per Second

0

1

2

Multi-Layer PCB, JEDEC Standard Test Boards

49.4°C/W

44.2°C/W

42.1°C/W

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Reliability Information

Table 7.  vs. Air Flow Table for a 6-Lead Ceramic 5mm x 7mm Package

JA

_JAvs. Air Flow

Meters per Second

0

1

2

Multi-Layer PCB, JEDEC Standard Test Boards

49.4°C/W

44.2°C/W

42.1°C/W

Transistor Count

The transistor count for IDT8N4DV85 is: 47,414

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Package Outline and Package Dimensions

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products

The programmable VCXO and XO devices support a variety of

devices options such as the output type, number of default frequen-

cies, internal crystal frequency, power supply voltage, ambient

temperature range and the frequency accuracy. The device options,

default frequencies and default VCXO pull range must be specified at

the time of order and are programmed by IDT before the shipment.

The table below specifies the available order codes, including the

device options and default frequency configurations. Example part

number: the order code 8N3QV01FG-0001CDI specifies a

contains a 114.285MHz internal crystal as frequency source,

industrial temperature range, a lead-free (6/6 RoHS) 6-lead ceramic

5mm x 7mm x 1.55mm package and is factory-programmed to the

default frequencies of 100MHz, 122.88MHz, 125MHz and

156.25MHz and to the VCXO pull range of min. 100 ppm.

Other default frequencies and order codes are available from IDT on

request. For more information on available default frequencies, see

the FemtoClock NG Ceramic-Package XO and VCXO Ordering

Product Information document.

programmable, quad default-frequency VCXO with a voltage supply

of 2.5V, a LVPECL output, a 50 ppm crystal frequency accuracy,

Part/Order Number

8N X X XXX X X - dddd XX X X

Shipping Package

8: Tape & Reel

(no letter): Tray

FemtoClock NG

I/O Identifier

Ambient Temperature Range

“I”: Industrial: (T_A= -40°C to 85°C)

(no letter) : (T_A= 0°C to 70°C)

0: LVCMOS

3: LVPECL

4: LVDS

Package Code

CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm

Number of Default Frequencies

S: 1: Single

D: 2: Dual

Q: 4: Quad

Default-Frequency and VCXO Pull Range

See document FemtoClock NG Ceramic-Package XO and VCXO

Ordering Product Information.

dddd

f_XTAL(MHz) PLL feedback

Use for

VCXO, XO

XO

Part Number

0000 to 0999

1000 to 1999

2000 to 2999

114.285

Fractional

Integer

OE fct. at

Function #pins

100.000

Fractional

XO

001

003

V01

V03

V75

V76

V85

085

270

271

272

273

XO

10

6

OE@2

OE@1

OE@2

OE@1

OE@2

nOE@2

—

Last digit = L: configuration pre-programmed and not

VCXO

XO

Die Revision

C

6

Option Code (Supply Voltage and Frequency-Stability)

6

OE@1

OE@2

nOE@2

nOE@1

A: V_CC= 3.3V 5%, 100ppm

B: V_CC= 2.5V 5%, 100ppm

XO

6

XO

6

E: V_CC= 3.3V 5%,

F: V_CC= 2.5V 5%,

K: V_CC= 3.3V 5%,

L: V_CC= 2.5V 5%,

50ppm

20ppm

20ppm

XO

6

XO

6

NOTE: For order information, also see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document.

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IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Device Marking

Table 8. Device Marking

Industrial Temperature Range (T_A= -40°C to 85°C)

Commercial Temperature Range (T_A= 0°C to 70°C)

IDT8N4DV85yC-

ddddCDI

IDT8N4DV85yC-

ddddCD

Marking

x = Number of Default Frequencies, y = Option Code, dddd = Default-Frequency and VCXO Pull Range.

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LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

Revision History Sheet

Rev

Table

Page

Description of Change

Date

4

Absolute Maximum Rating - corrected Package Thermal Impedance.

T6

T7

12

Power Considerations - corrected Thermal Resistance table, updated Junction

Temperature calculation.

A

4/27/12

13

Corrected Air Flow table.

T4D

T4E

4

5

3.3V LVDS DC Characteristics Table - updated specs.

2.5V LVDS DC Characteristics Table - updated specs.

Per PCN #N1206-02.

B

8/22/12

5A

6

RMS Phase Jitter, Test Conditions, fixed test conditions: 

15.576MHz – 100MHz, to 15.576MHz  f_out 100MHz, 

100MHz – 500MHz, to 100MHz < f_out500MHz, 

500MHz – 1300MHz, to 500MHz < f_out1300MHz

11/20/2013

IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013

17

IDT8N4DV75 Data Sheet

LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO

We’ve Got Your Timing Solution

6024 Silver Creek Valley Road Sales

Technical Support Sales

800-345-7015 (inside USA)

netcom@idt.com

San Jose, California 95138

+408-284-8200 (outside USA) +480-763-2056

Fax: 408-284-2775

www.IDT.com/go/contactIDT

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any

license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-

cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third

party owners.

型号:	8N4DV85EC-1078CD
生命周期：	Active
Reach Compliance Code：	compliant
风险等级：	5.64
振荡器类型：	LVDS
Base Number Matches：	1

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