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产品型号8T39S11ANLGI的Datasheet PDF文件预览

Crystal or Differential-to-Differential  
Clock Fanout Buffer  
8T39S11A  
Datasheet  
General Description  
Features  
The 8T39S11A is a high-performance clock fanout buffer. The input  
clock can be selected from two differential inputs or one crystal input.  
The internal oscillator circuit is automatically disabled if the crystal  
input is not selected. The crystal pin can be driven by a single-ended  
clock.The selected signal is distributed to ten differential outputs  
which can be configured as LVPECL, LVDS or HSCL outputs. In  
addition, an LVCMOS output is provided. All outputs can be disabled  
into a high-impedance state. The device is designed for a signal  
fanout of high-frequency, low phase-noise clock and data signal. The  
outputs are at a defined level when inputs are open or tied to ground.  
It is designed to operate from a 3.3V or 2.5V core power supply, and  
either a 3.3V or 2.5V output operating supply.  
Two differential reference clock input pairs  
Differential input pairs can accept the following differential input  
levels: LVPECL, LVDS, HCSL, HSTL or Single Ended  
Crystal Input accepts 10MHz to 40MHz Crystal or Single Ended  
Clock  
Maximum Output Frequency  
LVPECL - 2GHz  
LVDS  
HCSL  
- 2GHz  
- 250MHz  
LVCMOS - 250MHz  
Two banks, each has five differential output pairs that can be  
configured as LVPECL or LVDS or HCSL  
One single-ended reference output with synchronous enable to  
avoid clock glitch  
Output skew: 80ps (maximum)  
(Bank A and Bank B at the same output level)  
Part-to-part skew: 200ps (typical)  
Additive RMS phase jitter @ 156.25MHz:  
5.6fs RMS (10kHz - 1 MHz), typical @ 3.3V/ 3.3V  
34.7fs RMS (12kHz - 20MHz), typical @ 3.3V/ 3.3V  
Supply voltage modes:  
VDD/VDDO  
3.3V/3.3V  
3.3V/2.5V  
2.5V/2.5V  
-40°C to 85°C ambient operating temperature  
Lead-free (RoHS 6) packaging  
©2015 Integrated Device Technology, Inc.  
1
December 17, 2015  
8T39S11A Datasheet  
Block Diagram  
Pin Assignment for 7mm x 7mm 48-Lead VFQFN Package  
36 35 34 33 32 31 30 29 28 27 26 25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
GND  
GND  
nc  
SMODEB0  
REF_SEL1  
nCLK0  
SMODEB1  
nCLK1  
CLK1  
CLK0  
REF_SEL0  
GND  
VDD  
8T39S11A  
GND  
XTAL_OUT  
XTAL_IN  
VDD  
REFOUT  
VDDOREF  
OE_SE  
SMODEA1  
GND  
SMODEA0  
GND  
1
2
3
4
5
6
7
8
9
10 11 12  
©2015 Integrated Device Technology, Inc.  
2
December 17, 2015  
8T39S11A Datasheet  
Pin Description and Pin Characteristic Tables  
1
Table 1: Pin Descriptions  
Number  
Name  
QA0  
Type  
Description  
1
2
Output  
Output  
Output  
Output  
Power  
Output  
Output  
Power  
Output  
Output  
Output  
Output  
Power  
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.  
Output supply pins for Bank QA outputs.  
nQA0  
QA1  
3
4
nQA1  
VDDOA  
QA2  
5
6
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.  
Output supply pins for Bank QA outputs.  
7
nQA2  
VDDOA  
QA3  
8
9
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.  
Power supply ground.  
10  
11  
12  
13  
nQA3  
QA4  
nQA4  
GND  
Output driver select for Bank A outputs. See Table 8 for function.  
LVCMOS/LVTTL interface levels.  
14  
SMODEA0  
Input  
Pulldown  
15  
16  
17  
18  
VDD  
XTAL_IN  
XTAL_OUT  
GND  
Power  
Input  
Power supply pin.  
Crystal oscillator interface.  
Crystal oscillator interface.  
Power supply ground.  
Output  
Power  
Input clock selection. LVCMOS/LVTTL interface levels.  
See Table 3 for function.  
19  
20  
21  
22  
23  
REF_SEL0  
CLK0  
Input  
Input  
Input  
Input  
Input  
Pulldown  
Pullup/  
Pulldown  
Non-inverting differential clock. Internally biased to 0.33VDD.  
Inverting differential clock. Internally biased to 0.4VDD.  
Pullup/  
Pulldown  
nCLK0  
Input clock selection. LVCMOS/LVTTL interface levels.  
See Table 3 for function.  
REF_SEL1  
SMODEB0  
Pulldown  
Pulldown  
Output driver select for Bank B outputs. See Table 9 for function.  
LVCMOS/LVTTL interface levels.  
24  
25  
26  
27  
28  
29  
30  
31  
32  
GND  
nQB4  
QB4  
Power  
Output  
Output  
Output  
Output  
Power  
Output  
Output  
Power  
Power supply ground.  
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.  
Output supply pins for Bank QB outputs.  
nQB3  
QB3  
VDDOB  
nQB2  
QB2  
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.  
Output supply pins for Bank QB outputs.  
VDDOB  
©2015 Integrated Device Technology, Inc.  
3
December 17, 2015  
8T39S11A Datasheet  
1
Table 1: Pin Descriptions (Continued)  
Number  
33  
Name  
nQB1  
QB1  
nQB0  
QB0  
GND  
nc  
Type  
Description  
Output  
Output  
Output  
Output  
Power  
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.  
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.  
Power supply ground.  
34  
35  
36  
37  
38  
Unused  
No connect pin.  
Output driver select for Bank B outputs. See Table 9 for function.  
LVCMOS/LVTTL interface levels.  
39  
40  
41  
SMODEB1  
nCLK1  
Input  
Input  
Input  
Pulldown  
Pullup/  
Pulldown  
Inverting differential clock. Internally biased to 0.4VDD.  
Pullup/  
Pulldown  
CLK1  
Non-inverting differential clock. Internally biased to 0.33VDD.  
42  
43  
44  
45  
46  
VDD  
Power  
Power  
Output  
Power  
Input  
Power supply pin.  
GND  
Power supply ground.  
REFOUT  
VDDOREF  
OE_SE  
Single-ended reference clock output. LVCMOS/LVTTL interface levels.  
Output supply pin for REFOUT output.  
Pulldown Output enable. LVCMOS/LVTTL interface levels. See Table 4.  
Output driver select for Bank A outputs. See Table 8 for function.  
LVCMOS/LVTTL interface levels.  
47  
SMODEA1  
Input  
Pulldown  
48  
GND  
Power  
Power  
Power supply ground.  
ePad  
GND_EP  
Connect ePad to ground to ensure proper heat dissipation.  
NOTE 1. Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2: Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
OE_SE,  
SMODEx[1:0],  
REF_SEL[1:0]  
Input  
Capacitance  
CIN  
2
pF  
RPULLDOWN Input Pulldown Resistor  
50  
100  
75  
k  
k  
k  
pF  
CLK0, CLK1  
Input Pullup  
Resistor  
RPULLUP  
nCLK0, nCLK1  
REFOUT  
Power  
VDDOREF = 3.465V  
5.3  
CPD  
Dissipation  
Capacitance  
REFOUT  
V
DDOREF = 2.625V  
6.3  
pF  
REFOUT  
REFOUT  
VDDOREF = 3.3V  
52  
63  
Output  
Impedance  
ROUT  
V
DDOREF = 2.5V  
©2015 Integrated Device Technology, Inc.  
4
December 17, 2015  
8T39S11A Datasheet  
Function Tables  
1
Table 3: REF_SELx Function Table  
Control Input  
Table 4: OE_SE Function Table  
OE_SE  
REFOUT  
REF_SEL[1:0]  
Selected Input Reference Clock  
0 (default)  
1
High-Impedance  
Enabled  
00 (default)  
CLK0, nCLK0  
CLK1, nCLK1  
XTAL  
01  
10  
11  
NOTE 1. Synchronous output enable to avoid clock glitch.  
XTAL  
Table 5: Input/Output Operation Table, OE_SE  
Input Status  
Output State  
REFOUT  
OE_SE  
0 (default)  
1
REF_SEL [1:0]  
Don’t care  
CLKx and nCLKx  
Don’t Care  
High Impedance  
Fanout crystal oscillator  
10 or 11  
Don’t Care  
CLK0 and nCLK0 are both open circuit  
CLK0 and nCLK0 are tied to ground  
CLK0 is high, nCLK0 is low  
Logic Low  
Logic Low  
Logic High  
Logic Low  
Logic Low  
Logic Low  
Logic High  
Logic Low  
1
1
00 (default)  
CLK0 is low, nCLK0 is high  
CLK1 and nCLK1 are both open circuit  
CLK1 and nCLK1 are tied to ground  
CLK1 is high, nCLK1 is low  
01  
CLK1 is low, nCLK1 is high  
Table 6: Input/Output Operation Table, SMODEA  
Input Status  
Output State  
QA[4:0], nQA[4:0]  
High Impedance  
SMODEA[1:0]  
11  
REF_SEL[1:0]  
Don’t care  
10 or 11  
CLKx and nCLKx  
Don’t Care  
00, 01 or 10  
Don’t Care  
Fanout crystal oscillator  
QA[4:0] = Low  
nQA[4:0] = High  
CLK0 and nCLK0 are both open circuit  
CLK0 and nCLK0 are tied to ground  
CLK0 is high, nCLK0 is low  
QA[4:0] = Low  
nQA[4:0] = High  
00, 01 or 10  
00 (default)  
QA[4:0] = High  
nQA[4:0] = Low  
QA[4:0] = Low  
nQA[4:0] = High  
CLK0 is low, nCLK0 is high  
QA[4:0] = Low  
nQA[4:0] = High  
CLK1 and nCLK1 are both open circuit  
CLK1 and nCLK1 are tied to ground  
CLK1 is high, nCLK1 is low  
QA[4:0] = Low  
nQA[4:0] = High  
00, 01 or 10  
01  
QA[4:0] = High  
nQA[4:0] = Low  
QA[4:0] = Low  
nQA[4:0] = High  
CLK1 is low, nCLK1 is high  
©2015 Integrated Device Technology, Inc.  
5
December 17, 2015  
8T39S11A Datasheet  
Table 7: Input/Output Operation Table, SMODEB  
Input Status  
Output State  
SMODEB[1:0]  
11  
REF_SEL[1:0]  
Don’t care  
10 or 11  
CLKx and nCLKx  
Don’t Care  
QB[4:0], nQB[4:0]  
High Impedance  
00, 01 or 10  
Don’t Care  
Fanout crystal oscillator  
QB[4:0] = Low  
nQB[4:0] = High  
CLK0 and nCLK0 are both open circuit  
CLK0 and nCLK0 are tied to ground  
CLK0 is high, nCLK0 is low  
QB[4:0] = Low  
nQB[4:0] = High  
00, 01 or 10  
00 (default)  
QB[4:0] = High  
nQB[4:0] = Low  
QB[4:0] = Low  
nQB[4:0] = High  
CLK0 is low, nCLK0 is high  
QB[4:0] = Low  
nQB[4:0] = High  
CLK1 and nCLK1 are both open circuit  
CLK1 and nCLK1 are tied to ground  
CLK1 is high, nCLK1 is low  
QB[4:0] = Low  
nQB[4:0] = High  
00, 01 or 10  
01  
QB[4:0] = High  
nQB[4:0] = Low  
QB[4:0] = Low  
nQB[4:0] = High  
CLK1 is low, nCLK1 is high  
Table 8: Output Level Selection Table, QA[0:4], nQA[0:4]  
SMODEA1  
SMODEA0  
Output Type  
LVPECL (default)  
LVDS  
0
0
1
1
0
1
0
1
HCSL  
High-Impedance  
Table 9: Output Level Selection Table, QB[0:4], nQB[0:4]  
SMODEB1  
SMODEB0  
Output Type  
LVPECL (default)  
LVDS  
0
0
1
1
0
1
0
1
HCSL  
High-Impedance  
©2015 Integrated Device Technology, Inc.  
6
December 17, 2015  
8T39S11A Datasheet  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or  
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VDD  
4.6V  
Inputs, VI  
XTAL_IN  
0V to 2V  
Other Inputs  
-0.5V to VDD + 0.5V  
Outputs, VO, (HCSL, LVCMOS)  
-0.5V to VDDOX1 + 0.5V  
Outputs, IO, (LVPECL)  
Continuous Current  
Surge Current  
50mA  
100mA  
Outputs, IO, (LVDS)  
Continuous Current  
Surge Current  
10mA  
15mA  
Junction Temperature  
125°C  
Storage Temperature, TSTG  
-65°C to 150°C  
NOTE 1. VDDOX denotes VDDOA, VDDOB and VDDOREF.  
DC Electrical Characteristics  
Table 10: Power Supply DC Characteristics, V = V  
= V  
= V  
= 3.3V 5%, GND = 0V, T = -40°C to 85°C  
DDOREF A  
DD  
DDOA  
DDOB  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VDD  
Power Supply Voltage  
3.135  
3.3  
3.465  
V
VDDOA,  
VDDOB, VDDOREF  
Output Supply Voltage  
3.135  
3.3  
3.465  
V
IDD  
Power Supply Current  
Output Supply Current1  
Power Supply Current  
Power Supply Current  
Output Supply Current2  
SMODEA/B[1:0] = 01  
SMODEA/B[1:0] = 01  
101  
215  
168  
93  
114  
242  
195  
106  
93  
mA  
mA  
mA  
mA  
mA  
I
DDOA + IDDOB  
IEE  
SMODEA/B[1:0] = 00 (default)  
SMODEA/B[1:0] = 10  
IDD  
IDDOA + IDDOB  
SMODEA/B[1:0] = 10  
81  
NOTE 1. Differential outputs are terminated with 100.  
NOTE 2. Differential outputs are running at 250MHz and floating.  
©2015 Integrated Device Technology, Inc.  
7
December 17, 2015  
8T39S11A Datasheet  
Table 11: Power Supply DC Characteristics,  
V
= 3.3V 5%, V  
= V  
= V  
= 2.5V 5%, GND = 0V, T = -40°C to 85°C  
DDOREF A  
DD  
DDOA  
DDOB  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VDD  
Power Supply Voltage  
3.135  
3.3  
3.465  
V
VDDOA,  
VDDOB, VDDOREF  
Output Supply Voltage  
2.375  
2.5  
2.625  
V
IDD  
Power Supply Current  
Output Supply Current1  
Power Supply Current  
Power Supply Current  
Output Supply Current2  
SMODEA/B[1:0] = 01  
SMODEA/B[1:0] = 01  
101  
215  
167  
93  
114  
242  
194  
106  
77  
mA  
mA  
mA  
mA  
mA  
I
DDOA + IDDOB  
IEE  
IDD  
DDOA + IDDOB  
SMODEA/B[1:0] = 00 (default)  
SMODEA/B[1:0] = 10  
I
SMODEA/B[1:0] = 10  
66  
NOTE 1. Differential outputs are terminated with 100.  
NOTE 2. Differential outputs are running at 250MHz and floating.  
Table 12: Power Supply DC Characteristics, V = V  
= V  
= V  
= 2.5V 5%, GND = 0V, T = -40°C to 85°C  
DDOREF A  
DD  
DDOA  
DDOB  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VDD  
Power Supply Voltage  
2.375  
2.5  
2.625  
V
VDDOA,  
VDDOB, VDDOREF  
Output Supply Voltage  
2.375  
2.5  
2.625  
V
IDD  
Power Supply Current  
Output Supply Current1  
Power Supply Current  
Power Supply Current  
Output Supply Current2  
SMODEA/B[1:0] = 01  
SMODEA/B[1:0] = 01  
90  
207  
153  
74  
102  
234  
174  
84  
mA  
mA  
mA  
mA  
mA  
I
DDOA + IDDOB  
IEE  
IDD  
DDOA + IDDOB  
SMODEA/B[1:0] = 00 (default)  
SMODEA/B[1:0] = 10  
I
SMODEA/B[1:0] = 10  
65  
77  
NOTE 1. Differential outputs are terminated with 100.  
NOTE 2. Differential outputs are running at 250MHz and floating.  
Table 13: LVCMOS/LVTTL DC Characteristics,  
V
= 3.3V 5%, 2.5V 5%, V  
= 3.3V 5% or 2.5V 5%, GND = 0V, T = -40°C to 85°C  
DD  
DDOREF A  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
VDD + 0.3  
VDD + 0.3  
0.8  
Units  
VDD = 3.3V 5%  
2
V
V
V
V
VIH  
VIL  
Input High Voltage  
VDD = 2.5V 5%  
1.7  
-0.3  
-0.3  
VDD = 3.3V 5%  
VDD = 2.5V 5%  
OE_SE,  
Input Low Voltage  
SMODEA[1:0],  
SMODEB[1:0],  
REF_SEL[1:0]  
0.7  
Input  
High Current  
IIH  
IIL  
VDD = VIN = 3.465V or 2.625V  
150  
µA  
µA  
Input  
Low Current  
VDD = 3.465V or 2.625V, VIN = 0V  
VDDOREF= 3.3V 5%: IOH = -1mA  
-5  
2.6  
1.8  
V
V
Output  
High Voltage  
VOH  
V
DDOREF = 2.5V 5%: IOH = -1mA  
REFOUT  
Output  
Low Voltage  
VDDOREF = 3.3V 5% or 2.5V 5%:  
VOL  
0.5  
V
IOL = 1mA  
©2015 Integrated Device Technology, Inc.  
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December 17, 2015  
8T39S11A Datasheet  
Table 14: Differential DC Characteristics, V = 3.3V 5% or 2.5V 5%, GND = 0V, T = -40°C to 85°C  
DD  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input  
IIH  
CLK[0:1],  
nCLK[0:1]  
VDD = VIN = 3.465V or 2.625V  
150  
µA  
High Current  
Input  
IIL  
CLK[0:1],  
nCLK[0:1]  
VDD = 3.465V or 2.625V,  
VIN = 0V  
-150  
0.240  
µA  
V
Low Current  
VPP  
Peak-to-Peak Input Voltage1  
1.3  
Common Mode Input  
Voltage1 2  
VCMR  
GND + 0.5  
VDD – 0.85  
V
NOTE 1. Input voltage should not be less than -0.3V, and greater than VDD.  
NOTE 2. Common mode voltage is defined as the crosspoint.  
1
Table 15: LVPECL DC Characteristics, V  
= V  
= 3.3V 5%, GND = 0V, T = -40°C to 85°C  
DDOB A  
DDOA  
Symbol Parameter  
Test Conditions  
Minimum  
VDDOX – 1.4  
VDDOX – 2.0  
Typical  
Maximum  
VDDOX – 0.8  
VDDOX – 1.6  
Units  
VOH  
VOL  
Output High Voltage2  
Output Low Voltage2  
V
V
Peak-to-Peak Output  
Voltage Swing  
VSWING  
0.6  
1.0  
V
NOTE 1. VDDOX denotes VDDOA and VDDOB.  
NOTE 2. Outputs terminated with 50to VDDOX – 2V.  
1
Table 16: LVPECL DC Characteristics,  
Symbol Parameter  
V
= V  
= 2.5V 5%, GND = 0V, T = -40°C to 85°C  
DDOA  
DDOB A  
Test Conditions  
Minimum  
VDDOX – 1.4  
VDDOX – 2.0  
Typical  
Maximum  
VDDOX – 0.8  
VDDOX – 1.6  
Units  
VOH  
VOL  
Output High Voltage2  
Output Low Voltage2  
V
V
Peak-to-Peak Output  
Voltage Swing  
VSWING  
0.4  
1.0  
V
NOTE 1. VDDOX denotes VDDOA and VDDOB.  
NOTE 2. Outputs terminated with 50to VDDOX – 2V.  
Table 17: LVDS DC Characteristics, V  
= V  
= 3.3V 5%, GND = 0V, T = -40°C to 85°C  
DDOB A  
DDOA  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
mV  
mV  
V
VOD  
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
247  
454  
VOD  
VOS  
50  
1.025  
1.375  
VOS  
VOS Magnitude Change  
50  
mV  
Table 18: LVDS DC Characteristics,  
Symbol Parameter  
V
= V  
= 2.5V 5%, GND = 0V, T = -40°C to 85°C  
DDOA  
DDOB A  
Test Conditions  
Minimum  
Typical  
50  
Maximum  
Units  
mV  
mV  
V
VOD  
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
247  
454  
VOD  
VOS  
1.025  
1.375  
VOS  
VOS Magnitude Change  
50  
mV  
©2015 Integrated Device Technology, Inc.  
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December 17, 2015  
8T39S11A Datasheet  
Table 19: Crystal Characteristics  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Mode of Oscillation  
Frequency  
Fundamental  
10  
40  
50  
7
MHz  
Equivalent Series Resistance (ESR)  
Shunt Capacitance  
Capacitive Loading (CL)  
pF  
12  
18  
pF  
©2015 Integrated Device Technology, Inc.  
10  
December 17, 2015  
8T39S11A Datasheet  
AC Electrical Characteristics  
1 2  
Table 20: AC Characteristics, V = V  
= V  
= V  
= 3.3V 5%, GND = 0V, T = -40°C to 85°C  
DD  
DDOA  
DDOB  
DDOREF  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
2000  
Units  
MHz  
MHz  
MHz  
LVDS, LVPECL  
Outputs  
fOUT  
Output Frequency HCSL Outputs  
250  
LVCMOS  
Outputs  
250  
Clock Frequency = 156.25MHz;  
Input Clock from 8T49NS010A,  
Input Clock Jitter = 86.6fs;  
SMODEA/B[1:0] = 00  
Buffer Additive Phase Jitter, RMS:  
Integration Range 12kHz - 20MHz  
REF_SEL[1:0] = 00 or 01  
34.7  
5.6  
fs  
fs  
tjit  
Clock Frequency = 156.25MHz;  
Input Clock from 8T49NS010A,  
Input Clock Jitter = 60.8fs;  
SMODEA/B[1:0] = 00  
Buffer Additive Phase Jitter, RMS:  
Integration Range 10kHz - 1MHz  
REF_SEL[1:0] = 00 or 01  
LVPECL Outputs  
-159.1  
-157.0  
-156.0  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Offset Freq. >10MHz;  
156.25MHz Clock Freq.  
NF  
Noise Floor  
LVDS Outputs  
HCSL Outputs  
RMS Phase Jitter; 25MHz Integration  
Range: 100Hz - 1MHz  
tjit(Ø)  
tPD  
REF_SEL[1:0] = 10 or 113  
0.176  
ps  
CLK0, nCLK0 or  
SMODEA/B[1:0] = 00  
SMODEA/B[1:0] = 01  
SMODEA/B[1:0] = 10  
0.28  
0.28  
0.90  
0.75  
0.75  
2.65  
80  
ns  
ns  
Propagation  
Delay4  
CLK1, nCLK1 to  
any Qx, nQx  
Outputs  
ns  
tsk(o)  
tsk(pp)  
VOH  
Output Skew5 6  
ps  
Part-to-Part Skew6 7  
Voltage High8 9  
200  
ps  
HCSL Outputs  
HCSL Outputs  
TA = 25°CDC Measurement,  
RT = 50to GND  
CL 5pF  
520  
920  
150  
mV  
VOL  
Voltage Low8 10  
-150  
mV  
mV  
Absolute Crossing  
Voltage8 11 12  
VCROSS  
160  
460  
140  
4.0  
HCSL Outputs  
HCSL Outputs  
HCSL Outputs  
RT = 50to GND  
CL 5pF  
Total Variation of  
VCROSS over all  
Edges8 11 13  
VCROSS  
mV  
Rise/Fall  
0.6  
V/ns  
Edge Rate3 14 15  
LVPECL Outputs  
LVDS Outputs  
HCSL Outputs  
REFOUT  
20% to 80%  
20% to 80%  
150  
150  
400  
450  
300  
300  
650  
750  
55  
ps  
ps  
ps  
ps  
%
Output  
Rise/Fall Time  
tR / tF  
20% to 80%  
20% to 80%  
with Crystal Input  
45  
45  
odc  
Output Duty Cycle16  
with External 50%/ 50%  
Duty Cycle Clock Input  
55  
%
MUX_ISOLATION MUX Isolation  
156.25MHz  
75  
dB  
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the de-  
vice is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after  
thermal equilibrium has been reached under these conditions.  
NOTE 2. All LVDS and LVPECL parameters characterized up to 1.5GHz. HCSL parameters characterized up to 250MHz.  
©2015 Integrated Device Technology, Inc.  
11  
December 17, 2015  
8T39S11A Datasheet  
NOTE 3. Measurement taken from differential waveform.  
NOTE 4. Measured from the differential input crosspoint to the differential output crosspoint.  
NOTE 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cros-  
spoint.  
NOTE 6. This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency  
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cros-  
spoint  
NOTE 8. Measurement taken from single-ended waveform.  
NOTE 9. Defined as the maximum instantaneous voltage including overshoot.  
NOTE 10. Defined as the minimum instantaneous voltage including undershoot.  
NOTE 11. Measured at crosspoint where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.  
NOTE 12. Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all crosspoint  
for this measurement.  
NOTE 13. Measured from -150mV to +150mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the  
measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.  
NOTE 14. Measured from -150mV to +150mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the  
measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.  
NOTE 15. Measured at 100MHz.  
NOTE 16. Measured for the following frequencies: 25MHz, 100MHz, 125MHz, 156.25MHz, 312.5MHz, 400MHz, and 644.5313MHz.  
©2015 Integrated Device Technology, Inc.  
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December 17, 2015  
8T39S11A Datasheet  
1 2  
Table 21: AC Characteristics, V = 3.3V 5%, V  
= V  
= V  
= 2.5V 5%, GND = 0V, T = -40°C to 85°C  
DD  
DDOA  
DDOB  
DDOREF  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical Maximum  
Units  
MHz  
MHz  
MHz  
LVDS, LVPECL  
Outputs  
2000  
250  
fOUT  
Output Frequency HCSL Outputs  
LVCMOS  
Outputs  
250  
Clock Frequency = 156.25MHz;  
Input Clock from 8T49NS010A,  
Input Clock Jitter = 86.8fs;  
SMODEA/B[1:0] = 00  
Buffer Additive Phase Jitter, RMS:  
Integration Range 12kHz - 20MHz  
REF_SEL[1:0] = 00 or 01  
36.7  
6.6  
fs  
fs  
tjit  
Clock Frequency = 156.25MHz;  
Input Clock from 8T49NS010A,  
Input Clock Jitter = 60.8fs;  
SMODEA/B[1:0] = 00  
Buffer Additive Phase Jitter, RMS:  
Integration Range 10KHz - 1MHz  
REF_SEL[1:0] = 00 or 01  
LVPECL  
-159.1  
-157.0  
-155.7  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Offset Freq. >10MHz;  
156.25MHz Clock Freq.  
NF  
Noise Floor  
LVDS  
HCSL  
RMS Phase Jitter; 25MHz  
Integration Range: 100Hz - 1MHz  
tjit(Ø)  
tPD  
REF_SEL[1:0] = 10 or 113  
0.191  
ps  
CLK0, nCLK0 or  
SMODEA/B[1:0] = 00  
SMODEA/B[1:0] = 01  
SMODEA/B[1:0] = 10  
0.225  
0.275  
0.9  
0.80  
ns  
ns  
Propagation  
Delay4  
CLK1, nCLK1 to  
any Qx, nQx  
Outputs  
0.80  
2.80  
ns  
tsk(o)  
tsk(pp)  
VOH  
Output Skew5 6  
Part-to-Part Skew6 7  
Voltage High8 9  
80  
ps  
200  
ps  
HCSL Outputs  
HCSL Outputs  
TA = 25°CDC Measurement,  
RT = 50to GND  
CL 5pF  
520  
920  
mV  
VOL  
Voltage Low8 10  
-150  
150  
460  
mV  
mV  
Absolute Crossing  
Voltage8 11 12  
VCROSS  
HCSL Outputs  
HCSL Outputs  
HCSL Outputs  
160  
RT = 50to GND  
CL 5pF  
Total Variation of  
VCROSS over all  
Edges8 11 13  
VCROSS  
140  
4.0  
mV  
Rise/Fall  
0.6  
V/ns  
ps  
Edge Rate3 14 15  
LVPECL  
Outputs  
20% to 80%  
20% to 80%  
150  
150  
300  
300  
LVDS  
Outputs  
Output  
Rise/Fall Time  
ps  
tR / tF  
HCSL Outputs  
REFOUT  
20% to 80%  
20% to 80%  
400  
450  
650  
750  
55  
ps  
ps  
%
with Crystal Input  
45  
45  
odc  
Output Duty Cycle16  
with external 50%/ 50%  
Duty Cycle Clock Input  
55  
%
MUX_ISOLATION MUX Isolation  
156.25MHz  
75  
dB  
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the  
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications  
after thermal equilibrium has been reached under these conditions.  
NOTE 2. All LVDS and LVPECL parameters characterized up to 1.5GHz. HCSL parameters characterized up to 250MHz.  
©2015 Integrated Device Technology, Inc.  
13  
December 17, 2015  
8T39S11A Datasheet  
NOTE 3. Measurement taken from differential waveform.  
NOTE 4. Measured from the differential input crosspoint to the differential output crosspoint.  
NOTE 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cros-  
spoint.  
NOTE 6. This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency  
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cros-  
spoint  
NOTE 8. Measurement taken from single-ended waveform.  
NOTE 9. Defined as the maximum instantaneous voltage including overshoot.  
NOTE 10. Defined as the minimum instantaneous voltage including undershoot.  
NOTE 11. Measured at crosspoint where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.  
NOTE 12. Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all cros-  
spoint for this measurement.  
NOTE 13. Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in  
Vcross for any particular system.  
NOTE 14. Measured from -150mV to +150mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the  
measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.  
NOTE 15. Measured at 100MHz.  
NOTE 16. Measured for the following frequencies: 25MHz, 100MHz, 125MHz, 156.25MHz, 312.5MHz, 400MHz, and 644.5313MHz.  
©2015 Integrated Device Technology, Inc.  
14  
December 17, 2015  
8T39S11A Datasheet  
1 2  
Table 22: AC Characteristics, V = V  
= V  
= V  
= 2.5V 5%, GND = 0V, T = -40°C to 85°C  
DD  
DDOA  
DDOB  
DDOREF  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
2000  
Units  
MHz  
MHz  
MHz  
LVDS, LVPECL  
Outputs  
fOUT  
Output Frequency HCSL Outputs  
250  
LVCMOS  
Outputs  
250  
Clock Frequency = 156.25MHz;  
Input Clock from 8T49NS010A,  
Input Clock Jitter = 86.8fs;  
SMODEA/B[1:0] = 00  
Buffer Additive Phase Jitter, RMS:  
Integration Range 12kHz - 20MHz  
REF_SEL[1:0] = 00 or 01  
37.1  
fs  
tjit  
Clock Frequency = 156.25MHz;  
Input Clock from 8T49NS010A,  
Input Clock Jitter = 60.8fs;  
SMODEA/B[1:0] = 00  
Buffer Additive Phase Jitter, RMS:  
Integration Range 10kHz - 1MHz  
REF_SEL[1:0] = 00 or 01  
9.0  
fs  
RMS Phase Jitter; 25MHz Integration  
Range: 100Hz - 1MHz  
tjit(Ø)  
NF  
REF_SEL[1:0] = 10 or 113  
0.371  
ps  
LVPECL  
-159  
-157  
-155  
dBc/Hz  
dBc/Hz  
dBc/Hz  
ns  
Offset Freq. >10MHz;  
156.25MHz Clock Freq.  
Noise Floor  
LVDS  
HCSL  
CLK0, nCLK0 or  
CLK1, nCLK1 to  
any Qx, nQx  
Outputs  
SMODEA/B[1:0] = 00  
SMODEA/B[1:0] = 01  
SMODEA/B[1:0] = 10  
0.275  
0.275  
0.9  
0.75  
0.75  
2.80  
80  
Propagation  
Delay4  
ns  
tPD  
ns  
tsk(o)  
tsk(pp)  
VOH  
Output Skew5 6  
ps  
Part-to-Part Skew6 7  
Voltage High8 9  
200  
ps  
HCSL Outputs  
HCSL Outputs  
TA = 25°CDC Measurement,  
RT = 50to GND  
CL 5pF  
520  
920  
150  
mV  
VOL  
Voltage Low8 10  
-150  
mV  
mV  
Absolute Crossing  
Voltage8 11 12  
VCROSS  
HCSL Outputs  
HCSL Outputs  
HCSL Outputs  
160  
460  
140  
RT = 50to GND  
CL 5pF  
Total Variation of  
VCROSS over all  
Edges8 11 13  
VCROSS  
mV  
Rise/Fall  
0.6  
4.0  
V/ns  
ps  
Edge Rate3 14 15  
LVPECL  
Outputs  
20% to 80%  
150  
300  
Output  
Rise/Fall Time  
LVDS Outputs  
HCSL Outputs  
REFOUT  
20% to 80%  
20% to 80%  
150  
400  
450  
300  
650  
750  
55  
ps  
ps  
ps  
%
tR / tF  
20% to 80%  
With Crystal Input  
45  
45  
odc  
Output Duty Cycle16  
With external 50%/ 50% Duty  
Cycle Clock Input  
55  
%
MUX_ISOLATION MUX Isolation  
156.25MHz  
75  
dB  
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the  
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications  
after thermal equilibrium has been reached under these conditions.  
NOTE 2. All LVDS and LVPECL parameters characterized up to 1.5GHz. HCSL parameters characterized up to 250MHz.  
©2015 Integrated Device Technology, Inc.  
15  
December 17, 2015  
8T39S11A Datasheet  
NOTE 3. Measurement taken from differential waveform.  
NOTE 4. Measured from the differential input crosspoint to the differential output crosspoint.  
NOTE 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cros-  
spoint.  
NOTE 6. This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency  
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cros-  
spoint  
NOTE 8. Measurement taken from single-ended waveform.  
NOTE 9. Defined as the maximum instantaneous voltage including overshoot.  
NOTE 10. Defined as the minimum instantaneous voltage including undershoot.  
NOTE 11. Measured at crosspoint where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.  
NOTE 12. Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all cros-  
spoint for this measurement.  
NOTE 13. Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in Vcross  
for any particular system.  
NOTE 14. Measured from -150mV to +150mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the  
measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.  
NOTE 15. Measured at 100MHz.  
NOTE 16. Measured for the following frequencies: 25MHz, 100MHz, 125MHz, 156.25MHz, 312.5MHz, 400MHz, and 644.5313MHz.  
©2015 Integrated Device Technology, Inc.  
16  
December 17, 2015  
8T39S11A Datasheet  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a  
specified offset from the fundamental frequency to the power value of  
the fundamental. This ratio is expressed in decibels (dBm) or a ratio  
of the power in the 1Hz band to the power in the fundamental. When  
the required offset is specified, the phase noise is called a dBc value,  
which simply means dBm at a specified offset from the fundamental.  
By investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the entire  
time record of the signal. It is mathematically possible to calculate an  
expected bit error rate given a phase noise plot.  
Additive Phase Jitter @ 156.25MHz  
12kHz to 20MHz = 34.7fs (typical)  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements have  
issues relating to the limitations of the measurement equipment. The  
noise floor of the equipment can be higher or lower than the noise  
floor of the device. Additive phase noise is dependent on both the  
noise floor of the input source and measurement equipment.  
The additive phase jitter for this device was measured using an IDT  
Clock Driver 8T49NS010A as an input source and Agilent E5052  
phase noise analyzer.  
©2015 Integrated Device Technology, Inc.  
17  
December 17, 2015  
8T39S11A Datasheet  
Applications Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
CLK/nCLK Inputs  
LVCMOS Output (REFOUT)  
For applications not requiring the use of the differential input, both  
CLK and nCLK can be left floating. Though not required, but for  
additional protection, 1kresistors can be tied from CLK to ground  
and nCLK to VDD.  
If LVCMOS output is not used, then disable the output and it can be  
left floating.  
LVPECL and HCSL Outputs  
Any unused output pairs can be left floating. We recommend that  
there is no trace attached.  
Crystal Inputs  
For applications not requiring the use of the crystal oscillator input,  
both XTAL_IN and XTAL_OUT can be left floating. Though not  
required, but for additional protection, a 1kresistor can be tied from  
XTAL_IN to ground.  
LVDS Outputs  
Any unused LVDS output pairs can be either left floating or  
terminated with 100across. If they are left floating, we recommend  
that there is no trace attached.  
LVCMOS Control Pins  
Differential Outputs  
All control pins have internal pulldowns; additional resistance is not  
required but can be added for additional protection. A 1kresistor  
can be used.  
If all the outputs of any bank are not used, then disable all outputs to  
High-Impedance.  
Crystal Input Interface  
The 8T39S11A has been characterized with 18pF parallel resonant  
crystals. The capacitor values, C1 and C2, shown in Figure 1 below  
were determined using an 18pF parallel resonant crystal and were  
chosen to minimize the ppm error. In addition, the recommended  
12pF parallel resonant crystal tuning is shown in Figure 2.The  
optimum C1 and C2 values can be slightly adjusted for different  
board layouts.  
XTAL_IN  
C1  
27pF  
X1  
18pF Parallel Crystal  
XTAL_OUT  
Power Up Ramp Sequence  
C2  
27pF  
This device has multiple supply pins dedicated for different blocks.  
Output power supplies VDDOx (VDDOA, VDDOB, VDDOREF) must ramp  
up before, or concurrently with core power supply VDD. All power  
supplies must ramp up in a linear fashion and monotonically. Both  
Figure 1: Crystal Input Interface  
VDDOA and VDDOB power supplies must be powered-up even when  
only one bank of outputs is in use.  
XTAL_IN  
C1  
15pF  
X1  
12pF Parallel Crystal  
XTAL_OUT  
C2  
15pF  
Figure 2: Crystal Input Interface  
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8T39S11A Datasheet  
Overdriving the XTAL Interface  
The XTAL_IN input can be overdriven by an LVCMOS driver or by one  
side of a differential driver through an AC coupling capacitor. The  
XTAL_OUT pin can be left floating. The amplitude of the input signal  
should be between 500mV and 1.8V and the slew rate should not be  
less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be  
reduced from full swing to at least half the swing in order to prevent  
signal interference with the power rail and to reduce internal noise.  
Figure 3 shows an example of the interface diagram for a high speed  
3.3V LVCMOS driver. This configuration requires that the sum of the  
output impedance of the driver (Ro) and the series resistance (Rs)  
equals the transmission line impedance. In addition, matched  
termination at the crystal input will attenuate the signal in half. This  
can be done in one of two ways. First, R1 and R2 in parallel should  
equal the transmission line impedance. For most 50applications,  
R1 and R2 can be 100. This can also be accomplished by removing  
R1 and changing R2 to 50. The values of the resistors can be  
increased to reduce the loading for a slower and weaker LVCMOS  
driver. Figure 4 shows an example of the interface diagram for an  
LVPECL driver. This is a standard LVPECL termination with one side  
of the driver feeding the XTAL_IN input. It is recommended that all  
components in the schematics be placed in the layout. Though some  
components might not be used, they can be utilized for debugging  
purposes. The datasheet specifications are characterized and  
guaranteed by using a quartz crystal as the input.  
VCC  
XTAL_OUT  
R1  
100  
C1  
Rs  
Zo = 50 ohms  
Ro  
XTAL_IN  
.1uf  
R2  
100  
Zo = Ro + Rs  
LVCMOS Driver  
Figure 3: General Diagram for LVCMOS Driver to XTAL Input Interface  
XTAL_OUT  
C2  
Zo = 50 ohms  
XTAL_I N  
.1uf  
Zo = 50 ohms  
R1  
50  
R2  
50  
LVPECL Driver  
R3  
50  
Figure 4: General Diagram for LVPECL Driver to XTAL Input Interface  
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8T39S11A Datasheet  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 5 shows how a differential input can be wired to accept single  
ended levels. The reference voltage V1= VDD/2 is generated by the  
bias resistors R1 and R2. The bypass capacitor (C1) is used to help  
filter noise on the DC bias. This bias circuit should be located as close  
to the input pin as possible. The ratio of R1 and R2 might need to be  
adjusted to position the V1in the center of the input voltage swing. For  
example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2  
value should be adjusted to set V1 at 1.25V. The values below are for  
when both the single ended swing and VDD are at the same voltage.  
This configuration requires that the sum of the output impedance of  
the driver (Ro) and the series resistance (Rs) equals the transmission  
line impedance. In addition, matched termination at the input will  
attenuate the signal in half. This can be done in one of two ways.  
First, R3 and R4 in parallel should equal the transmission line  
impedance. For most 50applications, R3 and R4 can be 100. The  
values of the resistors can be increased to reduce the loading for  
slower and weaker LVCMOS driver. When using single-ended  
signaling, the noise rejection benefits of differential signaling are  
reduced. Even though the differential input can handle full rail  
LVCMOS signaling, it is recommended that the amplitude be  
reduced. The datasheet specifies a lower differential amplitude,  
however this only applies to differential signals. For single-ended  
applications, the swing can be larger, however VIL cannot be less  
than -0.3V and VIH cannot be more than VDD + 0.3V. Suggest edge  
rate faster than 1V/ns. Though some of the recommended  
components might not be used, the pads should be placed in the  
layout. They can be utilized for debugging purposes. The datasheet  
specifications are characterized and guaranteed by using a  
differential signal.  
Figure 5: Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
©2015 Integrated Device Technology, Inc.  
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8T39S11A Datasheet  
3.3V Differential Clock Input Interface  
The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential  
signals. Both differential signals must meet the VPP and VCMR input  
requirements. Figure 6 to Figure 9 show interface examples for the  
CLK/nCLK input driven by the most common driver types. The input  
interfaces suggested here are examples only. Please consult with the  
vendor of the driver component to confirm the driver termination  
requirements.  
Figure 6: CLK/nCLK Input Driven by a  
3.3V LVPECL Driver  
Figure 8: CLK/nCLK Input Driven by a  
3.3V LVPECL Driver  
3.3V  
3.3V  
*R3  
*R4  
CLK  
nCLK  
Differential  
Input  
HCSL  
Figure 7: CLK/nCLK Input Driven by a 3.3V HCSL Driver  
Figure 9: CLK/nCLK Input Driven by a 3.3V LVDS Driver  
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8T39S11A Datasheet  
2.5V Differential Clock Input Interface  
The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential  
signals. Both differential signals must meet the VPP and VCMR input  
requirements. Figure 10 to Figure 13 show interface examples for the  
CLK/nCLK input driven by the most common driver types. The input  
interfaces suggested here are examples only. Please consult with the  
vendor of the driver component to confirm the driver termination  
requirements.  
Figure 10: CLK/nCLK Input Driven by a  
2.5V LVPECL Driver  
Figure 12: CLK/nCLK Input Driven by a  
2.5V LVPECL Driver  
2.5V  
2.5V  
Zo = 50  
Zo = 50  
*R3  
*R4  
33  
33  
CLK  
nCLK  
Differential  
Input  
HCSL  
R1  
R2  
50  
50  
*Optional R3 and R4 can be 0  
Figure 11: CLK/nCLK Input Driven by a  
2.5V LVDS Driver  
Figure 13: CLK/nCLK Input Driven by a  
2.5V HCSL Driver  
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8T39S11A Datasheet  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the  
termination impedance (ZT) is between 90and 132. The actual  
value should be selected to match the differential impedance (Z0) of  
your transmission line. A typical point-to-point LVDS design uses a  
100parallel resistor at the receiver and a 100differential  
transmission-line environment. In order to avoid any  
transmission-line reflection issues, the components should be  
surface mounted and must be placed as close to the receiver as  
possible. IDT offers a full line of LVDS compliant devices with two  
types of output structures: current source and voltage source. The  
standard termination schematic as shown in Figure 14 can be used  
with either type of output structure. Figure 15, which can also be used  
with both output types, is an optional termination with center tap  
capacitance to help filter common mode noise. The capacitor value  
should be approximately 50pF. If using a non-standard termination, it  
is recommended to contact IDT and confirm if the output structure is  
current source or voltage source type. In addition, since these  
outputs are LVDS compatible, the input receiver’s amplitude and  
common-mode input range should be verified for compatibility with  
the output.  
ZO ZT  
LVDS  
Driver  
LVDS  
ZT  
Receiver  
Figure 14: Standard LVDS Termination  
ZT  
2
ZO ZT  
LVDS  
Driver  
LVDS  
Receiver  
C
ZT  
2
Figure 15: Optional LVDS Termination  
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8T39S11A Datasheet  
Termination for 3.3V LVPECL Outputs  
The clock topology shown below is a typical termination for LVPECL  
outputs. The two different terminations mentioned are recommended  
only as guidelines.  
used for functionality. These outputs are designed to drive 50  
transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion.  
The differential outputs are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
3.3V  
R3  
R4  
125  
125  
3.3V  
3.3V  
Zo = 50  
+
_
Input  
Zo = 50  
R1  
84  
R2  
84  
Figure 16: 3.3V LVPECL Output Termination  
Figure 17: 3.3V LVPECL Output Termination  
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8T39S11A Datasheet  
Termination for 2.5V LVPECL Outputs  
Figure 18 and Figure 19 show examples of termination for 2.5V  
LVPECL driver. These terminations are equivalent to terminating 50  
to VDDO – 2V. For VDDO = 2.5V, the VDDO – 2V is very close to ground  
level. The R3 in Figure 19 can be eliminated and the termination is  
shown in Figure 20.  
2.5V  
VDDO = 2.5V  
2.5V  
2.5V  
VDDO = 2.5V  
R1  
R3  
50Ω  
250  
250  
+
50Ω  
50Ω  
+
50Ω  
2.5V LVPECL Driver  
R1  
50  
R2  
50  
2.5V LVPECL Driver  
R2  
62.5  
R4  
62.5  
R3  
18  
Figure 18: 2.5V LVPECL Driver Termination Example  
Figure 20: 2.5V LVPECL Driver Termination Example  
2.5V  
VDDO = 2.5V  
50Ω  
+
50Ω  
2.5V LVPECL Driver  
R1  
50  
R2  
50  
Figure 19: 2.5V LVPECL Driver Termination Example  
©2015 Integrated Device Technology, Inc.  
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December 17, 2015  
8T39S11A Datasheet  
Recommended Termination  
Figure 21 is the recommended source termination for applications  
where the driver and receiver will be on a separate PCBs. This  
termination is the standard for PCI Express™and HCSL output types.  
All traces should be 50impedance single-ended or 100  
differential.  
Rs  
0.5" Max  
L1  
0-0.2"  
L2  
1-14"  
L4  
0.5 - 3.5"  
L5  
22 to 33 +/-5%  
L1  
L2  
L4  
L5  
PCI Express  
Connector  
PCI Express  
Driver  
PCI Express  
Add-in Card  
0-0.2" L3  
L3  
49.9 +/- 5%  
Rt  
Figure 21: Recommended Source Termination (where the driver and receiver will be on separate PCBs)  
Figure 22 is the recommended termination for applications where a  
point-to-point connection can be used. A point-to-point connection  
contains both the driver and the receiver on the same PCB. With a  
matched termination at the receiver, transmission-line reflections will  
be minimized. In addition, a series resistor (Rs) at the driver offers  
flexibility and can help dampen unwanted reflections. The optional  
resistor can range from 0to 33. All traces should be 50  
impedance single-ended or 100differential.  
Rs  
0.5" Max  
L1  
0-18"  
L2  
0-0.2"  
L3  
0 to 33  
0 to 33  
L1  
L2  
L3  
PCI Express  
Driver  
49.9 +/- 5%  
Rt  
Figure 22: Recommended Termination (where a point-to-point connection can be used)  
©2015 Integrated Device Technology, Inc.  
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8T39S11A Datasheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 23. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Lead frame Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 23: P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
©2015 Integrated Device Technology, Inc.  
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8T39S11A Datasheet  
LVPECL Power Considerations  
This section provides information on power dissipation and junction temperature for the 8T39S11A.  
Equations and example calculations are also provided.  
LVPECL Power Considerations  
1. Power Dissipation.  
The total power dissipation for the 8T39S11A is the sum of the core power plus the power dissipated due to outputs switching.  
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.  
The Maximum current at 85°C is as follows:  
IEE_MAX = 186.34mA  
Power (core)MAX = IEE_MAX * VDD_MAX = 3.465V * 186.34mA = 645.67mW  
Power (outputs)MAX = 32mW/Loaded Output pair  
If all outputs are loaded, the total output power is 10 * 32mW = 320mW  
Max LVPECL Power Dissipation = 645.67mW + 320mW = 965.67mW  
LVCMOS Output Power Dissipation  
Static Power Dissipation:  
Power (static)_max = VDDOREF_max * IDDREF_max = 3.465V * 2mA = 6.93mW  
(IDDREF_max = 2mA)  
Dynamic Power Dissipation at 250MHz:  
Power (Dynamic)_max = CPD * fMAX * N * VDDOREF2 = 5.3pF * 250MHz * 1 * 3.4652 = 15.9mW  
LVCMOS Power Dissipation = 6.93mW + 15.9mW = 22.84mW  
Total Power Dissipation = 965.67mW + 22.84mW = 988.51mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 30.5°C/W per Table 23 below. Therefore, Tj for an ambient temperature of 85°C with all outputs  
switching is:  
85°C + 0.9885W * 30.5°C/W = 115.15°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 23: Thermal Resistance for 48-Lead VFQFN  
JA  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
30.5°C/W  
26.7°C/W  
23.9°C/W  
©2015 Integrated Device Technology, Inc.  
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8T39S11A Datasheet  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.  
LVPECL output driver circuit and termination are shown in Figure 24.  
Figure 24: LVPECL Driver Circuit and Termination  
VDDO  
Q1  
VOUT  
RL  
50Ω  
VDDO - 2V  
To calculate power dissipation per output pair due to loading, use the following equations which assume a 50load, and a termination voltage  
of VDDO – 2V.  
For logic high, VOUT = VOH_MAX = VDDO_MAX – 0.8V  
(VDDO_MAX – VOH_MAX) = 0.8V  
For logic low, VOUT = VOL_MAX = VDDO_MAX – 1.6V  
(VDDO_MAX – VOL_MAX) = 1.6V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – (VDDO_MAX – VOH_MAX))/RL] * (VDDO_MAX – VOH_MAX) =  
[(2V – 0.8V)/50] * 0.8V = 19.20mW  
Pd_L = [(VOL_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – (VDDO_MAX – VOL_MAX))/RL] * (VDDO_MAX – VOL_MAX) =  
[(2V – 1.6V)/50] * 1.6V = 12.80mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW  
©2015 Integrated Device Technology, Inc.  
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8T39S11A Datasheet  
LVDS Power Considerations  
This section provides information on power dissipation and junction temperature for the 8T39S11A.  
Equations and example calculations are also provided.  
LVDS Power Considerations  
1. Power Dissipation.  
The total power dissipation for the 8T39S11A is the sum of the core power plus the power dissipated due to outputs switching.  
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.  
The Maximum current at 85°C is as follows:  
IDD_MAX = 106.9mA  
IDDO_MAX = 221.5mA  
Max LVDS Power Dissipation = VDD_MAX * (IDD_MAX + IDDO_MAX) = 3.465V * (106.9mA + 221.5mA) = 1137.9mW  
LVCMOS Output Power Dissipation  
Static Power Dissipation:  
Power (static)_max = VDDOREF_max * IDDREF_max = 3.465V * 2mA = 6.93mW  
(IDDREF_max = 2mA)  
Dynamic Power Dissipation at 250MHz:  
Power (Dynamic)_max = CPD * fMAX * N * VDDOREF2 = 5.3pF * 250MHz * 1 * 3.4652 = 15.9mW  
LVCMOS Power Dissipation = 6.93mW + 15.9mW = 22.84mW  
Total Power Dissipation = 1137.9mW + 22.84mW = 1160.75mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 30.5°C/W per Table 24. Therefore, Tj for an ambient temperature of 85°C with all outputs switching  
is:  
85°C + 1.161W * 30.5°C/W = 120.4°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 24: Thermal Resistance for 48-Lead VFQFN  
JA  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
30.5°C/W  
26.7°C/W  
23.9°C/W  
©2015 Integrated Device Technology, Inc.  
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8T39S11A Datasheet  
HCSL Power Considerations  
This section provides information on power dissipation and junction temperature for the 8T39S11A.  
Equations and example calculations are also provided.  
HCSL Power Considerations  
1. Power Dissipation.  
The total power dissipation for the 8T39S11A is the sum of the core power plus the power dissipated due to outputs switching.  
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.  
The Maximum current at 85°C is as follows:  
IDD_MAX = 96.63mA  
IDDO_MAX = 85mA (Application Frequency = 250MHz)  
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDO_MAX) = 3.465V * (96.63mA + 85mA) = 629.35mW  
Power (outputs)MAX = 44.5mW/Loaded Output pair  
If all outputs are loaded, the total power is 10 * 44.5mW = 445mW  
Max HCSL Power Dissipation = 629.35mW + 445mW = 1074.35mW  
LVCMOS Output Power Dissipation  
Static Power Dissipation:  
Power (static)_max = VDDOREF_max * IDDREF_max = 3.465V * 2mA = 6.93mW  
(IDDREF_max = 2mA)  
Dynamic Power Dissipation at 250MHz:  
Power (Dynamic)_max = CPD * fMAX * N * VDDOREF2 = 5.3pF * 250MHz * 1 * 3.4652 = 15.9mW  
LVCMOS Power Dissipation = 6.93mW + 15.9mW = 22.84mW  
Total Power Dissipation = 1074.35mW + 22.84mW = 1097.19mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 30.5°C/W per Table 25. Therefore, Tj for an ambient temperature of 85°C with all outputs switching  
is:  
85°C + 1.097W * 30.5°C/W = 118.5°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 25: Thermal Resistance for 48-Lead VFQFN  
JA  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
30.5°C/W  
26.7°C/W  
23.9°C/W  
©2015 Integrated Device Technology, Inc.  
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8T39S11A Datasheet  
3. Calculations and Equations.  
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.  
HCSL output driver circuit and termination are shown in Figure 25.  
Figure 25: HCSL Driver Circuit and Termination  
VDDO  
IOUT = 17mA  
VOUT  
RREF  
=
475Ω 1%  
RL  
50Ω  
IC  
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,  
use the following equations which assume a 50load to ground.  
The highest power dissipation occurs when VDDO MAX.  
_
Power = (VDDO_MAX – VOUT) * IOUT  
,
since VOUT – IOUT * RL  
= (VDDO_MAX – IOUT * RL) * IOUT  
= (3.465V – 17mA * 50) * 17mA  
Total Power Dissipation per output pair = 44.5mW  
©2015 Integrated Device Technology, Inc.  
32  
December 17, 2015  
8T39S11A Datasheet  
Reliability Information  
Table 26: vs. Air Flow Table for a 48-Lead VFQFN  
JA  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
30.5°C/W  
26.7°C/W  
23.9°C/W  
Transistor Count  
The transistor count for 8T39S11A is: 10,283  
©2015 Integrated Device Technology, Inc.  
33  
December 17, 2015  
8T39S11A Datasheet  
48-Lead VFQFN Package Outline and Package Dimensions  
©2015 Integrated Device Technology, Inc.  
34  
December 17, 2015  
8T39S11A Datasheet  
48-Lead VFQFN Package Outline and Package Dimensions, continued  
©2015 Integrated Device Technology, Inc.  
35  
December 17, 2015  
8T39S11A Datasheet  
Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Tray  
Temperature  
-40°C to 85°C  
-40°C to 85°C  
8T39S11ANLGI  
8T39S11ANLGI8  
IDT8T39S11ANLGI  
IDT8T39S11ANLGI  
48-Lead VFQFN, Lead-Free  
48-Lead VFQFN, Lead-Free  
Tape & Reel  
©2015 Integrated Device Technology, Inc.  
36  
December 17, 2015  
8T39S11A Datasheet  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.idt.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications  
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein  
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,  
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners.  
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.  
Copyright ©2015 Integrated Device Technology, Inc. All rights reserved.  
配单直通车
8T3C10B05PA产品参数
型号:8T3C10B05PA
生命周期:Transferred
IHS 制造商:SOURIAU INC
Reach Compliance Code:unknown
风险等级:5.69
其他特性:STANDARD: MIL-DTL-38999, LOW PROFILE, POLARIZED
后壳类型:SOLID
主体/外壳类型:RECEPTACLE
连接器类型:MIL SERIES CONNECTOR
触点性别:MALE
耦合类型:BAYONET
DIN 符合性:NO
空壳:NO
环境特性:CORROSION/ENVIRONMENT/FLUID RESISTANT
滤波功能:NO
IEC 符合性:NO
MIL 符合性:YES
插接信息:MULTIPLE MATING PARTS AVAILABLE
混合触点:NO
安装类型:BOARD AND PANEL
选件:GENERAL PURPOSE
外壳面层:CADMIUM PLATED
外壳材料:ALUMINUM ALLOY
外壳尺寸:10
端接类型:SOLDER
触点总数:5
Base Number Matches:1
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