8T39S11A Datasheet
Pin Description and Pin Characteristic Tables
1
Table 1: Pin Descriptions
Number
Name
QA0
Type
Description
1
2
Output
Output
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Power
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pins for Bank QA outputs.
nQA0
QA1
3
4
nQA1
VDDOA
QA2
5
6
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pins for Bank QA outputs.
7
nQA2
VDDOA
QA3
8
9
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Power supply ground.
10
11
12
13
nQA3
QA4
nQA4
GND
Output driver select for Bank A outputs. See Table 8 for function.
LVCMOS/LVTTL interface levels.
14
SMODEA0
Input
Pulldown
15
16
17
18
VDD
XTAL_IN
XTAL_OUT
GND
Power
Input
Power supply pin.
Crystal oscillator interface.
Crystal oscillator interface.
Power supply ground.
Output
Power
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3 for function.
19
20
21
22
23
REF_SEL0
CLK0
Input
Input
Input
Input
Input
Pulldown
Pullup/
Pulldown
Non-inverting differential clock. Internally biased to 0.33VDD.
Inverting differential clock. Internally biased to 0.4VDD.
Pullup/
Pulldown
nCLK0
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3 for function.
REF_SEL1
SMODEB0
Pulldown
Pulldown
Output driver select for Bank B outputs. See Table 9 for function.
LVCMOS/LVTTL interface levels.
24
25
26
27
28
29
30
31
32
GND
nQB4
QB4
Power
Output
Output
Output
Output
Power
Output
Output
Power
Power supply ground.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pins for Bank QB outputs.
nQB3
QB3
VDDOB
nQB2
QB2
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pins for Bank QB outputs.
VDDOB
©2015 Integrated Device Technology, Inc.
3
December 17, 2015