AD9696/AD9698
PIN CONFIGURATIONS
Q1
OUT
(N/C)
Q1
OUT
(–V
S
)
GROUND (–IN
1
)
LATCH ENABLE 1 (+IN
1
)
N/C (+IN
2
)
–V
S
(–IN
2
)
–IN
1
(+V
S
)
+IN
1
(N/C)
1
2
3
4
5
6
7
8
TOP VIEW
(Not to Scale)
16 Q2
OUT
(LATCH ENABLE 1)
15 Q2
OUT
(GROUND)
14 GROUND (Q1
OUT
)
13
LATCH ENABLE 2 (Q1
OUT
)
+V
S
+IN
–IN
–V
S
1
2
3
4
TOP VIEW
(Not to Scale)
8
7
6
5
Q
OUT
Q
OUT
GROUND
LATCH
ENABLE
12 N/C (Q2
OUT
)
11 +V
S
(Q2
OUT
)
10 –IN
2
(GROUND)
9
+IN
2
(LATCH ENABLE 2)
AD9698KN/KQ/TQ
[AD9698KR/TZ PINOUTS SHOWN IN ( )]
AD9696KN/KR/KQ/TQ/TZ
Name
Q1
OUT
Q1
OUT
GROUND
LATCH
ENABLE 1
Function
One of two complementary outputs. Q1
OUT
will be at logic HIGH if voltage at +IN
1
is greater than voltage at
–IN
1
and LATCH ENABLE 1 is at logic LOW.
One of two complementary outputs. Q1
OUT
will be at logic HIGH if voltage at –IN
1
is greater than voltage at
+IN
1
and LATCH ENABLE 1 is at logic LOW.
Analog and digital ground return. All GROUND pins should be connected together and to a low impedance
ground plane near the comparator.
Output at Q1
OUT
will track differential changes at the inputs when LATCH ENABLE 1 is at logic LOW.
When LATCH ENABLE 1 is at logic HIGH, the output at Q1
OUT
will reflect the input state at the application of
the latch command, delayed by the Latch Enable Setup Time (t
S
). Since the architecture of the input stage (see
block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s)
within 1.7 ns after the latch. This is the Setup Time (t
S
); for guaranteed performance, t
S
must be 3 ns.
No internal connection to comparator.
Negative power supply connection; nominally –5.2 V.
Inverting input of differential input stage for Comparator #1.
Noninverting input of differential input stage for Comparator #1.
Noninverting input of differential input stage for Comparator #2.
Inverting input of differential input stage for Comparator #2.
Positive power supply connection; nominally +5 V.
Output at Q2
OUT
will track differential changes at the inputs when LATCH ENABLE 2 is at logic LOW.
When LATCH ENABLE 2 is at logic HIGH, the output at Q2
OUT
will reflect the input state at the application of
the latch command, delayed by the Latch Enable Setup Time (t
S
). Since the architecture of the input stage (see
block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s)
within 1.7 ns after the latch. This is the Setup Time (t
S
); for guaranteed performance, t
S
must be 3 ns.
One of two complementary outputs. Q2
OUT
will be at logic HIGH if voltage at –IN
2
is greater than voltage at
+IN
2
and LATCH ENABLE 2 is at logic LOW.
One of two complementary outputs. Q2
OUT
will be at logic HIGH if voltage at +IN
2
is greater than voltage at
–IN
2
and LATCH ENABLE 2 is at logic LOW.
N/C
–V
S
–IN
1
+IN
1
+IN
2
–IN
2
+V
S
LATCH
ENABLE 2
Q2
OUT
Q2
OUT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9696/AD9698 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
AD [ ANALOG DEVICES ]
