AD9696/AD9698
LATCH
ENABLE
LATCH
COMPARE
V
OS
TWO DIODES
ABOVE GROUND
t
H
DIFFERENTIAL
INPUT VOLTAGE
V
IN
t
PW (E)
t
S
V
OD
Q
50%
t
PD
t
PD (E)
Q
50%
t
S
– MINIMUM SETUP TIME (Typically 1.7ns)
t
H
– MINIMUM HOLD TIME (Typically 1.9ns)
t
PD
– INPUT TO OUTPUT DELAY
t
PD (E)
– LATCH ENABLE TO OUTPUT DELAY
t
PW (E)
– MINIMUM LATCH ENABLE PULSE WIDTH (Typically 2.5ns)
V
OS
– INPUT OFFSET VOLTAGE
V
OD
– OVERDRIVE VOLTAGE
AD9696/AD9698 Timing Diagram
DIE LAYOUT AND MECHANICAL INFORMATION
THEORY OF OPERATION
Die Dimensions AD9696 . . . . . . . . . . . . . 59×71×15 (± 2) mils
AD9698 . . . . . . . . . . . . 79×109×15 (± 2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4×4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V
S
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Refer to the block diagram of the AD9696/AD9698 compara-
tors. The AD9696 and AD9698 TTL voltage comparator archi-
tecture consists of five basic stages: input, latch, gain, level shift
and output. Each stage is designed to provide optimal perfor-
mance and make it easy to use the comparators.
The input stage operates with either a single +5-volt supply, or
with a +5-volt supply and a –5.2-volt supply. For optimum
power efficiency, the remaining stages operate with only a single
+5-volt supply. The input stage is an input differential pair
without the customary emitter follower buffers. This configura-
tion increases input bias currents but maximizes the input volt-
age range.
A latch stage allows the most recent output state to be retained
as long as the latch input is held high. In this way, the input to
the comparator can be changed without any change in the out-
put state. As soon as the latch enable input is switched to LOW,
the output changes to the new value dictated by the signal ap-
plied to the input stage.
The gain stage assures that even with small values of input volt-
age, there will be sufficient levels applied to the following stages
to cause the output to switch TTL states as required. A level
shift stage between the gain stage and the TTL output stage
guarantees that appropriate voltage levels are applied from the
gain stage to the TTL output stage.
Only the output stage uses TTL logic levels; this minimum use
of TTL circuits maximizes speed and minimizes power con-
sumption. The outputs are clamped with Schottky diodes to as-
sure that the rising and falling edges of the output signal are
closely matched.
The AD9696 and AD9698 represent the state of the art in high
speed TTL voltage comparators. Great care has been taken to
optimize the propagation delay dispersion performance. This as-
sures that the output delays will remain constant despite varying
levels of input overdrive. This characteristic, along with closely
matched rising and falling outputs, provides extremely consis-
tent results at previously unattainable speeds.
REV. B
–5–
AD [ ANALOG DEVICES ]
