Data Sheet
DIGITAL PERIPHERALS
3-PHASE PWM
Each ADuC7019/20/21/22/24/25/26/27/28/29 provides a flexible
and programmable, 3-phase pulse-width modulation (PWM)
waveform generator. It can be programmed to generate the
required switching patterns to drive a 3-phase voltage source
inverter for ac induction motor control (ACIM). Note that only
active high patterns can be produced.
The PWM generator produces three pairs of PWM signals on
the six PWM output pins (PWM0
H
, PWM0
L
, PWM1
H
, PWM1
L
,
PWM2
H
, and PWM2
L
). The six PWM output signals consist of
three high-side drive signals and three low-side drive signals.
The switching frequency and dead time of the generated PWM
patterns are programmable using the PWMDAT0 and PWMDAT1
MMRs. In addition, three duty-cycle control registers (PWMCH0,
PWMCH1, and PWMCH2) directly control the duty cycles of
the three pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMEN register. In addition,
three control bits of the PWMEN register permit crossover of
the two signals of a PWM pair. In crossover mode, the PWM
signal destined for the high-side switch is diverted to the comple-
mentary low-side output. The signal destined for the low-side
switch is diverted to the corresponding high-side output signal.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the inverter power
devices. In general, there are two common isolation techniques:
optical isolation using optocouplers and transformer isolation
using pulse transformers. The PWM controller permits mixing
of the output PWM signals with a high frequency chopping signal
to permit easy interface to such pulse transformers. The features
of this gate-drive chopping mode can be controlled by the
PWMCFG register. An 8-bit value within the PWMCFG
register directly controls the chopping frequency. High
frequency chopping can be independently enabled for the high-
side and low-side outputs using separate control bits in the
PWMCFG register.
The PWM generator can operate in one of two distinct modes:
single update mode or double update mode. In single update
mode, the duty cycle values are programmable only once per
PWM period so that the resulting PWM patterns are symmetrical
about the midpoint of the PWM period. In the double update
mode, a second updating of the PWM duty cycle values is
implemented at the midpoint of the PWM period.
In double update mode, it is also possible to produce asymmetrical
PWM patterns that produce lower harmonic distortion in 3-phase
PWM inverters. This technique permits closed-loop controllers
to change the average voltage applied to the machine windings
at a faster rate. As a result, faster closed-loop bandwidths are
achieved. The operating mode of the PWM block is selected by
a control bit in the PWMCON register. In single update mode,
ADuC7019/20/21/22/24/25/26/27/28/29
an internal synchronization pulse, PWMSYNC, is produced at
the start of each PWM period. In double update mode, an
additional PWMSYNC pulse is produced at the midpoint of
each PWM period.
The PWM block can also provide an internal synchronization
pulse on the PWM
SYNC
pin that is synchronized to the PWM
switching frequency. In single update mode, a pulse is produced
at the start of each PWM period. In double update mode, an
additional pulse is produced at the mid-point of each PWM period.
The width of the pulse is programmable through the PWMDAT2
register. The PWM block can also accept an external synchro-
nization pulse on the PWM
SYNC
pin. The selection of external
synchronization or internal synchronization is in the PWMCON
register. The SYNC input timing can be synchronized to the
internal peripheral clock, which is selected in the PWMCON
register. If the external synchronization pulse from the chip pin is
asynchronous to the internal peripheral clock (typical case), the
external PWMSYNC is considered asynchronous and should be
synchronized. The synchronization logic adds latency and jitter
from the external pulse to the actual PWM outputs. The size of
the pulse on the PWM
SYNC
pin must be greater than two core
clock periods.
The PWM signals produced by the ADuC7019/20/21/22/24/25/
26/27/28/29 can be shut off via a dedicated asynchronous PWM
shutdown pin, PWM
TRIP
. When brought low, PWM
TRIP
instanta-
neously places all six PWM outputs in the off state (high). This
hardware shutdown mechanism is asynchronous so that the
associated PWM disable circuitry does not go through any
clocked logic. This ensures correct PWM shutdown even in
the event of a core clock loss.
Status information about the PWM system is available to the user
in the PWMSTA register. In particular, the state of the PWM
TRIP
pin is available, as well as a status bit that indicates whether oper-
ation is in the first half or the second half of the PWM period.
40-Pin Package Devices
On the 40-pin package devices, the PWM outputs are not
directly accessible, as described in the General-Purpose
GPIO (see Table 78) via the PLA as shown in the following
example:
PWMCON = 0x1;
PWMDAT0 = 0x055F;
// enables PWM o/p
// PWM switching freq
// Configure Port Pins
GP4CON = 0x300;
// P4.2 as PLA output
GP3CON = 0x1;
// P3.0 configured as
// output of PWM0
//(internally)
// PWM0 onto P4.2
PLAELM8 = 0x0035;
PLAELM10 = 0x0059;
// P3.0 (PWM output)
// input of element 8
// PWM from element 8
Rev. F | Page 61 of 104
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