AD6311
1/8- to 1/16 Duty VFD Controller/Driver
Pin Descriptions
Symbol
D
IN
D
OUT
Name
Data input
Data output
No.
6
Description
STB
Strobe
CLK
OSC
Seg
1
/KS
1
to
Seg
12
/KS
12
Grid
1
to Grid
8
Seg
13
/Grid
16
to
Seg
20
/Grid
9
LED
1
to LED
5
KEY
1
to KEY
4
V
DD
V
SS
V
EE
SW
1
to SW
4
NC
Clock input
Oscillator pin
High-voltage output
High-voltage output (Grid)
High-voltage output (Segment/grid)
LED output
Key data input
Logic power
Logic ground
Pull-down level
Switch input
NC
Input serial data at rising edge of shift clock,
starting from the low order bit.
Output serial data at the falling edge of the shift
5
clock, starting from low order bit. This is N-ch
open-drain output pin.
Initializes serial interface at the rising or falling
edge of the AD6311. It then waits for reception of a
command. Data input after STB falling is
processed as a command. While command data is
9
processed, current processing is stopped, and the
serial interface is initialized. While STB is high,
CLK is ignored.
Reads serial data at the rising edge, and outputs
8
data at the falling edge.
Connect resistor in between this pin and Vdd to set
52
up the oscillation frequency.
Multi-function pins, Segment output pins (Dual
15 to 26
function as key scan source)
37 to 44 Grid output pins
27 to 32 These pins are selectable for segment or grid
35, 36
driving.
46 to 50 CMOS output
Data input to these pins is latched at the end of the
10 to 13
display cycle.
14, 33, 45 Logic power supply
51
34
1 to 4
7
Connect this pin to system GND.
Driver power supply
These pins constitute a 4-bit general-purpose input
port.
No connection
Ordering Information
AD6311X X X
Package
Q: QFP-52L
Lead
Blank: Normal
F: Lead Free
Packing
Blank : Tray
Anachip Corp.
www.anachip.com.tw
2/11
Rev. A5 Dec 29, 2003
ANACHIP [ ANACHIP CORP ]
