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CN8330 参数 Datasheet PDF下载

CN8330图片预览
型号: CN8330
PDF下载: 下载PDF文件 查看货源
内容描述: DS3 / E3成帧器与52 Mbps的HDLC控制器 [DS3/E3 Framer with 52 Mbps HDLC Controller]
分类和应用: 控制器
文件页数/大小: 101 页 / 571 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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2.0 Functional Description  
CN8330  
2.3 Transmitter Operation  
DS3/E3 Framer with 52 Mbps HDLC Controller  
In C-bit parity mode with internal sourcing of the C-bits, FEBE alarms are  
generated automatically in the transmitter when the receiver detects either a frame  
bit error or a C-bit parity error in an M-frame. The 3-bit FEBE pattern that is  
transmitted is contained in the FEBE Pattern Bit Field [FEBEC[3:1];CR04.2:0] of  
the Feature Control Register. Bit 2 is placed in the C1 position of subframe 4  
during the alarm condition, bit 1 is placed in the C2 position, and bit 0 is placed in  
the C3 position. When no alarm condition is present, the FEBE channel contains  
all ones. Therefore, to prevent disabling proper FEBE operation, the FEBE field  
should be written to any combination other than 111.  
An unframed, all-ones signal can be transmitted by setting both TxAlm0 and  
TxAlm1 to a 1 and ExtOvh cleared to a 0.  
In E3 mode, the AIS (unframed all-ones) is enabled by setting TxAlm0 high.  
The yellow alarm is enabled by setting TxAlm1 high. This causes the transmitted  
A-bit to be set to a one.  
2.3.6 Terminal Data Link Transmitter  
The terminal data link transmitter consists of the three C-bits in subframe 5 of the  
M-frame in DS3 mode or the N-bit in E3 mode and uses the LAPD protocol.  
When the Send Message bit [TxMsg;CR01.0] of the Terminal Data Link Control  
Register [CR01;0x01] is low, the data link transmitter is continuously sending idle  
flags (01111110). When high, message transmission is initiated. Transmission of  
the FCS bytes is controlled by the Send Frame Check Sequence bit  
[TxFCS;CR01.1]. If a nonstandard FCS is required, it may be loaded into the  
message buffer and transmitted as part of the message. A message in progress  
may be abandoned by setting the Abort Message bit [TxAbort;CR01.2]. This will  
cause an abort flag (11111110) to be transmitted, followed by idle flags, until the  
Send Message bit is reactivated. Two consecutive messages may share ending and  
beginning idle flags. The transmitter can be disabled by setting the Disable  
Terminal Data Link Transmission bit [DisTxTDL;CR01.6] to a one. This causes  
all ones to be sent in the data link bit positions.  
The terminal data link transmitter is under control of the C-Bit Parity  
Mode/Enable DLINT/SOURCELB (CBitP/DL;CR00.0), E3 Framing Mode  
[E3Frm;CR00.1], External C-Bit Insert, and Transmit Alarm Control bits in the  
Mode Control Register. In the Terminal Data Link Control Register, the  
transmitter is under the control of the TxMsg, TxFCS, TxAbort, Send Byte  
[TxByte[2:0];CR01.5:3], and DisTxTDL bits. An interrupt for use with data link  
operations is available on the DLINT/SOURCELB output pin and status bits for  
determining the interrupt source are located in the Data Link Interrupt Status  
Register [SR02;0x12].  
The framer mode must be set to either C-bit parity mode or E3 mode for  
terminal data link transmission to take place. In C-bit parity mode, the three  
C-bits in subframe 5 of the M-frame will be used for transmission. In E3 mode,  
the N-bit will be used for transmission. When E3 mode is selected, the CBitP/DL  
bit must also be set to enable interrupts on the DLINT/SOURCELB pin. If neither  
mode is set, terminal data link transmission will not take place. If the ExtCBit bit  
is set in E3 mode, terminal data link transmission will be disabled. In C-bit parity  
mode, ExtCBit has no effect on terminal data link transmission. Setting the  
Transmit Alarm Control [1,0] bits for transmission of AIS or all ones in either  
C-bit parity mode or E3 mode will disable transmission of the terminal data link.  
Transmission of yellow alarms or idle codes has no effect on terminal data link  
transmission.  
2-12  
Conexant  
100441E