CN8330
2.0 Functional Description
DS3/E3 Framer with 52 Mbps HDLC Controller
2.3 Transmitter Operation
If the framer is in a mode that allows data link transmission as described
previously, then the Terminal Data Link Control Register is the main control
register used for transmit data link operations. The DisTxTDL bit must be set low
to enable operation of the data link. If high, an all-ones signal will be transmitted
in the data link bit positions in the outgoing serial stream. With the data link
enabled, the TxMsg, TxFCS, and TxAbort bits control operation. The
TxByte[2:0] bits form a pointer to the Transmit Terminal Data Link Message
Buffer [TxTdl;0x30–0x37] used by the data link transmitter.
The transmitter implements an LAPD data link per CCITT standard Q.921.
The functions provided by the data link transmitter circuitry are transparency zero
stuffing, FCS generation, idle flag generation, and abort flag generation. The total
length of the message has no restrictions. Q.921 requires all messages be integral
numbers of 8-bit bytes. The transmitter can only transmit 8-bit bytes. Byte
transmission time for the transmitter is approximately 284 microseconds in C-bit
parity mode and approximately 357 microseconds in E3 mode.
The Transmit Terminal Data Link Message Buffer is an 8-byte buffer provided
for the transmit data link channel to minimize processor interruptions. Filling of
this buffer is accomplished by the processor in the same manner as writes to
control registers. This buffer can be read as well as written to verify contents. The
buffer is divided into two halves to reduce the real-time requirements on the
processor. The processor loads four bytes at a time, while the data link transmitter
reads from the other half of the buffer. This gives the processor at least 1 msec to
assemble the next four bytes of message for transmission before the next interrupt
is issued. Interrupts are issued each time the transmitter circuitry reaches a 4-byte
buffer boundary.
The transmitter must initialized with bits 0 through 6 of the Terminal Data
Link Control Register written to zero. This will enable the transmitter to send idle
flags on the data link. No interrupts are generated when the data link is sending
idle flags, thus no processor intervention is required until a message is to be sent.
2.3.6.1 Sending a
Message
Beginning with an idle channel, the processor writes the first four bytes of
message data to the Transmit Terminal Data Link Message Buffer. The first byte
of data to be transmitted should be written to address 0x30. The message is read
from the buffer in ascending order starting at address 0x30 and ending at address
0x37. The Least Significant Bit (LSB) in each byte is the first transmitted. This
buffer may be written well before the message is to be sent, if desired. After the
first block of data is present in the buffer memory, the processor writes to the
Terminal Data Link Control Register to begin transmission (TxMsg = 1,
TxByte[2:0] = 011, TxFCS = 0, TxAbort = 0). The 3-bit TxByte[2:0] field is
functionally split into two parts. The Most Significant Bit (MSB) indicates to the
transmitter circuitry which half of the buffer to read from next. The two LSBs
indicate the stop location, i.e., where the last message byte is located. When the
new controls are latched by the transmitter circuitry, the processor will be
interrupted for the next set of controls. Now, the processor has up to 1 msec to
write a new set of controls to the control register. The processor may now also
write the next block of data to the next half of the message buffer.
When the end of a message is reached, or in the event of a short message, there
may not be exactly 4 bytes remaining. In this case, the processor writes the
remaining data to the message buffer as usual. The processor now must write the
highest location used to the TxByte[2:0] field. Also, the TxFCS bit is set to 1.
This causes the FCS to be sent after this last block of data.
100441E
Conexant
2-13
CONEXANT [ CONEXANT SYSTEMS, INC ]
