2.0 Functional Description
CN8330
2.3 Transmitter Operation
DS3/E3 Framer with 52 Mbps HDLC Controller
When this set of controls is latched, the processor will be interrupted. At this
time, a new message may be sent, or the TxMsg bit may be set to zero to send idle
flags. If a new message is to be sent immediately, the next half of the transmit
buffer can be written, and the Terminal Data Link Control Register optioned
accordingly. This will result in only one idle flag being transmitted between
messages. If there is no new message ready, the processor must write TxMsg to
zero. If this is not done within 1 msec, undefined data will be transmitted.
2.3.6.2 Aborting a
Message
To abort a message in progress, the controller writes the TxAbort bit to one in the
Terminal Data Link Control Register. The transmitter will finish sending the
message byte in progress, then transmit an abort flag (11111110). After writing
the abort signal to the control register, a second write may follow immediately to
cause the transmitter to go to the idle condition, or to transmit another message.
In the latter case, the abort flag will be followed by one idle flag, and then the new
message will begin. If the second write is not performed, the formatter will
continue to transmit abort flags until instructed otherwise.
2.3.6.3 Transmitter
Interrupts
The transmitter generates an interrupt when it has latched the present set of
controls and is ready for a new set. There will not be any interrupts during the
transmission of idle flags. Therefore, to start a message from an idle condition,
the first half of the buffer and the proper control bits are written by the processor.
When the circuit latches these controls internally, an interrupt will immediately
be issued for the next set of control bits. The processor then has up to 1 msec (4
byte periods) to respond to the interrupt. The Data Link Interrupt Status Register
[SR02;0x12] indicates the source of the interrupt but not the cause. The controller
software must know from message context what response is required. The
interrupt is an active low level, not a pulse. The interrupt will be cleared upon the
writing of the Terminal Data Link Control Register. A write operation must be
performed to clear the current interrupt and prevent missing later interrupts.
If the interrupt is a mid-message interrupt, a new data link control word must
be written, with bytes equal to the ending location of the next message block. The
MSB of TxByte[2:0] will inform the transmit circuitry which half of the buffer to
read next.
Interrupts from the Terminal Data Link Transmitter will appear in the
Transmit Terminal Data Link Interrupt bit [TxTDLItr;SR02.3]. Interrupts must be
enabled to appear on DLINT/SOURCELB by setting the CBitP/DL bit to a 1 in
the Mode Control Register in either C-bit parity or E3 mode.
2-14
Conexant
100441E
CONEXANT [ CONEXANT SYSTEMS, INC ]
