CX82100 Home Network Processor Data Sheet
Tables
Table 1-1. CX82100 Order Numbers, Part Numbers, and Supported Features .................................................................1-1
Table 2-1. CX82100-11/-12/-51/-52 HNP Pin Signals – 196-Pin FPBGA..........................................................................2-4
Table 2-2. CX82100-41/-42 HNP Pin Signals – 196-Pin FPBGA.......................................................................................2-7
Table 2-3. CX82100 HNP Pin Signal Definitions ..............................................................................................................2-8
Table 2-4. CX82100 HNP Input/Output Type Descriptions .............................................................................................2-16
Table 2-5. CX82100 HNP DC Electrical Characteristics ..................................................................................................2-17
Table 2-6. CX82100 HNP Operating Conditions.............................................................................................................2-18
Table 2-7. CX82100 HNP Absolute Maximum Ratings...................................................................................................2-18
Table 2-8. CX82100 HNP Power Consumption ..............................................................................................................2-18
Table 2-9. CX82100 HNP Recommended GPIO and Host Signal Use.............................................................................2-19
Table 2-10. CX82100 HNP Definitions of Recommended GPIO and Host Signals ..........................................................2-20
Table 3-1. Starting Addresses for Mapping ASB Slaves...................................................................................................3-3
Table 3-2. Starting Addresses for Mapping APB Slaves...................................................................................................3-3
Table 3-3. ARM Exception Vector Addresses...................................................................................................................3-3
Table 4-1. DMA Channel Definition for DMAC..................................................................................................................4-1
Table 4-2. DMA Requests for APB Peripherals ................................................................................................................4-2
Table 4-3. DMAC Registers..............................................................................................................................................4-3
Table 4-4. Cluster Descriptor Table..................................................................................................................................4-7
Table 4-5. Received Data Packet......................................................................................................................................4-8
Table 5-1. Host Master Mode Signals..............................................................................................................................5-2
Table 5-2. Chip Select Address Ranges ...........................................................................................................................5-3
Table 5-3. Timing for Host Master Mode Read Operation Based on a 100 MHz BCLK (CX82100-11/-12/-51/-52)............5-6
Table 5-4. Timing for Host Master Mode Write Operation Based on a 100 MHz BCLK (CX82100-11/-12/-51/-52)...........5-7
Table 5-5. Timing for Host Master Mode Read Operation Based on a 100 MHz BCLK (CX82100-41/-42) ......................5-10
Table 5-6. Timing for Host Master Mode Write Operation Based on a 100 MHz BCLK (CX82100-41/-42)......................5-11
Table 5-7. Host Master Mode Registers.........................................................................................................................5-12
Table 6-1. EMC SDRAM Interface Signal Descriptions.....................................................................................................6-2
Table 6-2. PC100 Compliant Mode Register ....................................................................................................................6-2
Table 6-3. Available SDRAM Vendors..............................................................................................................................6-3
Table 6-4. Allowed SDRAM Configurations......................................................................................................................6-4
Table 6-5. SDRAM Throughput........................................................................................................................................6-5
Table 6-6. HNP to SDRAM/SRAM Interface Signal Mapping............................................................................................6-7
Table 6-7. EMC Register..................................................................................................................................................6-8
Table 7-1. Parameterized Values Implemented in EMAC..................................................................................................7-3
Table 7-2. Transmit Descriptor Format..........................................................................................................................7-11
Table 7-3. Transmit Status Format ................................................................................................................................7-12
Table 7-4. Setup Frame Buffer Format...........................................................................................................................7-17
Table 7-5. Imperfect Address Filtering Setup Frame Format ..........................................................................................7-19
Table 7-6. Hash Index Generated Using Ethernet CRC Algorithm...................................................................................7-20
Table 7-7. Address Filtering Mode.................................................................................................................................7-22
Table 7-8. Definition of RMAC Receive Status ...............................................................................................................7-24
xii
Conexant Proprietary and Confidential Information
101306C
CONEXANT [ CONEXANT SYSTEMS, INC ]
