CX82100 Home Network Processor Data Sheet
12.5
Timer Registers.........................................................................................................................................................12-3
12.5.1
Timer 1 Counter Register (TM_Cnt1: 0x00350020) ...................................................................................12-3
12.5.2
Timer 2 Counter Register (TM_Cnt2: 0x00350024) ...................................................................................12-3
12.5.3
Timer 3 Counter Register (TM_Cnt3: 0x00350028) ...................................................................................12-4
12.5.4
Timer 4 Counter Register (TM_Cnt4: 0x0035002C) ...................................................................................12-4
12.5.5
Timer 1 Limit Register (TM_Lmt1: 0x00350030).......................................................................................12-4
12.5.6
Timer 2 Limit Register (TM_Lmt2: 0x00350034).......................................................................................12-4
12.5.7
Timer 3 Limit Register (TM_Lmt3: 0x00350038).......................................................................................12-5
12.5.8
Timer 4 Limit Register (TM_Lmt4: 0x0035003C).......................................................................................12-5
PLL Normal Mode .....................................................................................................................................................13-3
Generated Clocks ......................................................................................................................................................13-3
PLL Register Memory Map........................................................................................................................................13-5
PLL Registers............................................................................................................................................................13-5
13.4.1
FCLK PLL Register (PLL_F: 0x00350068)..................................................................................................13-5
13.4.2
BCLK PLL Register (PLL_B: 0x0035006C) ................................................................................................13-6
13.4.3
Low Power Mode Register (LPMR: 0x00350014)......................................................................................13-7
PLL Programming.....................................................................................................................................................13-8
Watchdog Timer Mode ..............................................................................................................................................13-9
PLL Bypass Mode .....................................................................................................................................................13-9
Register Type Definition ............................................................................................................................................14-1
Interface Registers Sorted by Supported Function.....................................................................................................14-2
Interface Registers Sorted by Address.......................................................................................................................14-6
13 Clock Generation Interface Description.............................................................................................. 13-1
13.1
13.2
13.3
13.4
13.5
13.6
13.7
14.1
14.2
14.3
14 Register Map Summary ..................................................................................................................... 14-1
101306C
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