CY22393, CY22394, CY22395
Addr S2 (1,0)
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
111
110
101
100
011
b7
b6
b5
b4
b3
b2
b1
b0
PLL1_Q[7:0]
PLL1_P[7:0]
DivSel
PLL1_En
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
DivSel
PLL1_En
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
DivSel
PLL1_En
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
DivSel
PLL1_En
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
DivSel
PLL1_En
PLL1_LF[2:0]
PLL1_PO
PLL1_P[9:8]
PLL1_PO
PLL1_P[9:8]
PLL1_PO
PLL1_P[9:8]
PLL1_PO
PLL1_P[9:8]
PLL1_PO
PLL1_P[9:8]
Serial Bus Programming Protocol and Timing
The CY22393, CY22394 and CY22395 have a 2-wire serial
interface for in-system programming. They use the SDAT and
SCLK pins, and operate up to 400 kbit/s in Read or Write mode.
Except for the data hold time, it is compliant with the I
2
C bus
standard. The basic Write serial format is as follows:
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is illus-
trated in
Data Valid
Data is valid when the clock is HIGH, and can only be transi-
tioned when the clock is LOW as illustrated in
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in
Start Sequence - Start Frame is indicated by SDAT going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).
Stop Sequence - Stop Frame is indicated by SDAT going HIGH
when SCLK is HIGH. A Stop Frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Default Startup Condition for the CY22393/94/95
The default (programmed) condition of each device is generally
set by the distributor, who programs the device using a customer
specified JEDEC file produced by CyClocksRT, Cypress’s propri-
etary development software. Parts shipped by the factory are
blank and unprogrammed. In this condition, all bits are set to 0,
all outputs are tri-stated, and the crystal oscillator circuit is active.
While users can develop their own subroutine to program any or
all of the individual registers as described in the following pages,
it may be easier to simply use CyClocksRT to produce the
required register setting file.
Acknowledge Pulse
During Write Mode the CY22393, CY22394, and CY22395
respond with an Acknowledge pulse after every eight bits. To do
this, they pull the SDAT line LOW during the N*9
th
clock cycle,
as illustrated in
transmitted). During Read Mode, the master generates the
acknowledge pulse after the data packet is read.
Device Address
The device address is a 7-bit value that is configured during Field
Programming. By programming different device addresses, two
or more parts are connected to the serial interface and can be
independently controlled. The device address is combined with
a read/write bit as the LSB and is sent after each start bit.
The default serial interface address is 69H, but must there be a
conflict with any other devices in your system, this can also be
changed using CyClocksRT.
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (ack = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the data word is received, the slave responds with another
acknowledge bit (ack = 0/LOW), and the master must end the
write sequence with a STOP condition.
Document #: 38-07186 Rev. *D
Page 9 of 19
CYPRESS [ CYPRESS SEMICONDUCTOR ]
