CY22393, CY22394, CY22395
OscDrv[1:0]
These bits control the crystal oscillator gain setting. These must
always be set according to
The parameters are the
Crystal Frequency, Internal Crystal Parasitic Resistance
(available from the manufacturer), and the OscCap setting
during crystal start up, which occurs when power is applied, or
after shutdown is released. If in doubt, use the next higher
setting.
Table 5. Crystal Oscillator Gain Settings
OscCap
8–15 MHz
15–20 MHz
20–25 MHz
25–30 MHz
00H–20H
60Ω
01
10
10
10
00
01
01
10
20H–30H
30Ω
01
01
10
10
60Ω
10
10
10
11
30H–40H
30Ω
01
10
10
11
60Ω
10
10
11
NA
Crystal Freq\ R 30Ω
For external reference, the use
Table 6. Osc Drv for External Reference
External Freq (MHz)
OscDrv[1:0]
1–25
00
25–50
01
50–90
10
90–166
11
Reserved
These bits must be programmed LOW for proper operation of the
device.
Serial Programming Bitmaps — Summary Tables
Addr
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
DivSel
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
b7
b6
Reserved
PLL3_En
Osc_Cap[5:0]
b5
b4
b3
b2
Reserved
PLL2_En
b7
ClkA_FS[0]
ClkA_FS[0]
ClkB_FS[0]
ClkB_FS[0]
ClkC_FS[0]
ClkD_FS[0]
ClkD_FS[2:1]
Clk{C,X}_ACAdj[1:0]
ClkX_DCAdj[1]
ClkC_FS[2:1]
Clk{A,B,D,E}_ACAdj[1:0]
Clk{D,E}_DCAdj[1]
PLL2_Q[7:0]
PLL2_P[7:0]
PLL2_LF[2:0]
PLL3_Q[7:0]
PLL3_P[7:0]
PLL3_LF[2:0]
PLL3_PO
PLL3_P[9:8]
Osc_Drv[1:0]
b1
b0
PLL2_PO
PLL2_P[9:8]
b6
b5
b4
b3
ClkA_Div[6:0]
ClkA_Div[6:0]
ClkB_Div[6:0]
ClkB_Div[6:0]
ClkC_Div[6:0]
ClkD_Div[6:0]
ClkB_FS[2:1]
PdnEn
Xbuf_OE
ClkC_DCAdj[1]
ClkA_FS[2:1]
ClkE_Div[1:0]
Clk{A,B}_DCAdj[1]
b2
b1
b0
Addr S2 (1,0)
40H
41H
42H
43H
44H
45H
46H
47H
48H
010
001
000
PLL1_Q[7:0]
PLL1_P[7:0]
DivSel
PLL1_En
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
DivSel
PLL1_En
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
DivSel
PLL1_En
PLL1_LF[2:0]
PLL1_PO
PLL1_P[9:8]
PLL1_PO
PLL1_P[9:8]
PLL1_PO
PLL1_P[9:8]
Document #: 38-07186 Rev. *D
Page 8 of 19
CYPRESS [ CYPRESS SEMICONDUCTOR ]
