CY7B991V
3.3V RoboClock
®
Figure 8. Multi-Function Clock Driver
REF
Z
0
20 MHz
DISTRIBUTION
CLOCK
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
80 MHz
INVERTED
LOAD
20 MHz
Z
0
LOAD
80 MHz
ZERO SKEW
80 MHz
SKEWED –3.125 ns (–4t
U
)
Z
0
LOAD
Z
0
LOAD
Figure 9. Board-to-Board Clock Distribution
LOAD
Z
0
L1
FB
SYSTEM
CLOCK
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Z
0
L2
Z
0
LOAD
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
REF
L3
Z
0
LOAD
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
shows the CY7B991V connected in series to construct a zero skew clock distribution tree between boards. Delays of the
downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay)
necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulate
low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in a
series.
Document Number: 38-07141 Rev. *D
Page 7 of 13
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