CY7B991V
3.3V RoboClock
®
Operational Mode Descriptions
Figure 3. Zero Skew and Zero Delay Clock Driver
REF
L1
Z
0
LOAD
SYSTEM
CLOCK
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
LENGTH L1 = L2 = L3 = L4
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
L2
Z
0
LOAD
L3
Z
0
L4
Z
0
LOAD
shows the LVPSCB configured as a zero skew clock buffer. In this mode, the CY7B991V is the basis for a low skew clock
distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and drive a terminated
transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency range
is selected with the FS pin. The low skew specification, coupled with the ability to drive terminated transmission lines (with impedances
as low as 50 ohms), enables efficient printed circuit board design.
Figure 4. Programmable Skew Clock Driver
REF
Z
0
LOAD
L1
SYSTEM
CLOCK
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
LOAD
L2
Z
0
LOAD
Z
0
L4
Z
0
LOAD
L3
shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between
outputs, the LVPSCB is programmed to stagger the timing of its
outputs. The four groups of output pairs are each programmed
to different output timing. Skew timing is adjusted over a wide
range in small increments with the appropriate strapping of the
function select pins. In this configuration, the 4Q0 output is sent
back to FB and configured for zero skew. The other three pairs
of outputs are programmed to yield different skews relative to the
feedback. By advancing the clock signal on the longer traces or
retarding the clock signal on shorter traces, all loads receive the
clock pulse at the same time.
shows the FB input connected to an output with 0 ns
skew (xF1, xF0 = MID) selected. The internal PLL synchronizes
the FB and REF inputs and aligns their rising edges to make
certain that all outputs have precise phase alignment.
Clock skews are advanced by ±6 time units (tU) when using an
output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed.
Since “Zero Skew”, +tU, and –tU are defined relative to output
groups, and the PLL aligns the rising edges of REF and FB, wider
output skews are created by proper selection of the xFn inputs.
For example, a +10 tU between REF and 3Qx is achieved by
connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID,
and 3F1 = High. (Since FB aligns at –4 tU, and 3Qx skews to +6
tU, a total of +10 tU skew is realized.) Many other configurations
are realized by skewing both the outputs used as the FB input
and skewing the other outputs.
Document Number: 38-07141 Rev. *D
Page 5 of 13
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