CY7C1041CV33
Switching Characteristics
Over the Operating Range
Parameter
Read Cycle
t
power[5]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
V
CC
(Typical) to the First Access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
Byte Enable to End of Write
7
10
7
7
0
0
7
5
0
3
5
8
Comm’l/Ind’l/Auto-A
Auto-E
0
6
12
8
8
0
0
8
6
0
3
6
10
0
6
15
10
10
0
0
10
7
0
3
7
10
0
10
5
3
5
0
12
6
7
0
7
20
10
10
0
0
10
8
0
3
8
0
8
Comm’l/Ind’l/Auto-A
Auto-E
0
5
3
6
0
15
7
0
6
3
7
0
20
8
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
10
5
100
10
10
3
12
6
7
0
7
3
8
0
8
100
12
12
3
15
7
100
15
15
3
20
8
8
ns
ns
ns
ns
ns
ns
ns
100
20
20
μs
ns
ns
ns
ns
ns
Description
-10
Min
Max
-12
Min
Max
-15
Min
Max
-20
Min
Max
Unit
Write Cycle
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V.
5. t
POWER
gives the minimum amount of time that the power supply is at typical V
CC
values until the first memory access is performed.
6. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
7. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of
±500
mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document Number: 38-05134 Rev. *I
Page 6 of 14
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