CY7C130/CY7C131
CY7C140/CY7C141
Pin Configuration
(continued
)
PLCC
Top View
BUSY
R
INTR
NC
BUSYL
R/W
L
CEL
VCC
CER
R/W
R
A0L
OEL
NC
INT
L
A0L
OEL
NC
INT
L
PQFP
Top View
BUSY
R
INTR
NC
BUSYL
R/W
L
CEL
VCC
CER
R/W
R
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
8
9
10
11
12
13
14
15
16
17
18
19
20
7 6 5 4 3 2 1 52 51 50 49 48 47
46
45
44
43
42
41
7C131
40
7C141
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O4L
I/O5L
I/O6L
I/O7L
NC
GND
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
52 5150 49 48 47 4645 44 43 42 41 40
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
7C131
7C141
1415 16 17 18 19 20 21 22 23 24 25 26
NC
GND
I/O0R
I/O1R
Pin Definitions
Left Port
CE
L
R/W
L
OE
L
A
0L
–A
11/12L
I/O
0L
–I/O
15/17L
INT
L
BUSY
L
V
CC
GND
CE
R
R/W
R
OE
R
A
0R
–A
11/12R
I/O
0R
–I/O
15/17R
INT
R
BUSY
R
Right Port
Chip Enable
Read/Write Enable
Output Enable
Address
Data Bus Input/Output
Interrupt Flag
Busy Flag
Power
Ground
Description
Selection Guide
7C131-15
7C141-15
Maximum Access Time
Maximum Operating Com’l/Ind
Current
Military
Maximum Standby
Current
Com’l/Ind
Military
15
190
75
7C131-25
7C141-25
25
170
65
7C130-30
7C131-30
7C140-30
7C141-30
30
170
65
7C130-35
7C131-35
7C140-35
7C141-35
35
120
170
45
65
7C130-45
7C131-45
7C140-45
7C141-45
45
120
170
45
65
7C130-55
7C131-55
7C140-55
7C141-55
55
110
120
35
45
mA
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O4L
I/O5L
I/O6L
I/O7L
Unit
ns
mA
Shaded areas contain preliminary information.
Note:
3. 15 and 25-ns version available only in PLCC/PQFP packages.
Document #: 38-06002 Rev. *D
Page 2 of 19
CYPRESS [ CYPRESS SEMICONDUCTOR ]
