CY7C1366B
CY7C1367B
CY7C1366B–Pin Definitions
Name
A
0
, A
1
, A
TQFP
37,36,32,33
,34,35,43,4
4,45,46,47,
48,49,50,81
,82,99,100
BGA
(2 Chip
Enable)
fBGA
I/O
Input-
Synchronous
Description
Address Inputs used to select one of the 256K
address locations.
Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
,
and CE
3 [2]
are sampled active. A1: A0 are fed to the
two-bit counter.
Byte Write Select Inputs, active LOW.
Qualified with
BWE to conduct byte writes to the SRAM. Sampled on
the rising edge of CLK.
Global Write Enable Input, active LOW.
When
asserted LOW on the rising edge of CLK, a global write
is conducted (ALL bytes are written, regardless of the
values on BW
X
and BWE).
Byte Write Enable Input, active LOW.
Sampled on the
rising edge of CLK. This signal must be asserted LOW
to conduct a byte write.
Clock Input.
Used to capture all synchronous inputs to
the device. Also used to increment the burst counter
when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW.
Sampled on the
rising edge of CLK. Used in conjunction with CE
2
and
CE
3[2]
to select/deselect the device. ADSP is ignored if
CE
1
is HIGH.
Chip Enable 2 Input, active HIGH.
Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and
CE
3[2]
to select/deselect the device.
R6,P6,A2,
P4,N4,A2,
C2,R2,3A, A10,B2,B10,
B3,C3,T3, P3,P4,P8,P9,
T4,A5,B5, P10,P11,R3,
C5,T5,A6, R4,R8,R9,
R10,R11
B6,C6,R6
BW
A,
BW
B
BW
C,
BW
D
GW
93,94,95,96 L5,G5,G3, B5,A5,A4,B4
L3
88
H4
B7
Input-
Synchronous
Input-
Synchronous
BWE
CLK
87
M4
A7
Input-
Synchronous
Input-
Clock
Input-
Synchronous
89
K4
B6
CE
1
98
E4
A3
CE
2
97
B2
B3
Input-
Synchronous
Input-
Synchronous
CE
3[2]
92
-
A6
OE
86
F4
B8
Chip Enable 3 Input, active LOW.
Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and
CE
2
to select/deselect the device.Not connected for
BGA. Where referenced, CE
3[2]
is assumed active
throughout this document for BGA.
Input-
Output Enable, asynchronous input, active LOW.
Asynchronous Controls the direction of the I/O pins. When LOW, the
I/O pins behave as outputs. When deasserted HIGH,
DQ pins are three-stated, and act as input data pins. OE
is masked during the first clock of a read cycle when
emerging from a deselected state.
Input-
Synchronous
Input-
Synchronous
Advance Input signal, sampled on the rising edge of
CLK, active LOW.
When asserted, it automatically
increments the address in a burst cycle.
Address Strobe from Processor, sampled on the
rising edge of CLK, active LOW.
When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE
1
is
deasserted HIGH.
Address Strobe from Controller, sampled on the
rising edge of CLK, active LOW.
When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
ADV
83
G4
A9
ADSP
84
A4
B9
ADSC
85
B4
A8
Input-
Synchronous
Document #: 38-05096 Rev. *B
Page 6 of 32
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