CY7C1366B
CY7C1367B
CY7C1366B–Pin Definitions
(continued)
Name
ZZ
TQFP
64
BGA
(2 Chip
Enable)
T7
fBGA
H11
I/O
Description
Input-
ZZ “sleep” Input, active HIGH.
When asserted HIGH
Asynchronous places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal
pull-down.
I/O-
Synchronous
Bidirectional Data I/O lines.
As inputs, they feed into
an on-chip data register that is triggered by the rising
edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses
presented during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP
X
are placed in a three-state
condition.
DQs, DQPs 52,53,56,57
,58,59,62,6
3,68,69,72,
73,74,75,
78,79,2,3,6,
7,8,9,
12,13,18,19
,22,23,24,2
5,28,29,51,
80,1,30
K6,L6,M6,
N6,K7,L7,
N7,P7,E6,
F6,G6,H6,
D7,E7,G7,
H7,D1,E1,
G1,H1,E2,
F2,G2,H2,
K1,L1,N1,
P1,K2,L2,
M2,N2,P6,
D6,D2,P2
M11,L11,K11,
J11,J10,K10,
L10,M10,D10
,E10,F10,G10
,D11,E11,F11,
G11,D1,E1,
F1,G1,D2,E2,
F2,G2,J1,K1,
L1,M1,J2,K2,
L2,M2,N11,
C11,C1,N1
V
DD
15,41,65,91 J2,C4,J4,R D4,D8,E4,E8,
4,J6
F4,F8,G4,G8,
H4,H8,J4,J8,
K4,K8,L4,L8,
M4,M8
17,40,67,90 D3,E3,F3,
H3,K3,M3,
N3,P3,D5,
E5,F5,H5,
K5,M5,N5,
P5
C4,C5,C6,C7,
C8,D5,D6,D7,
E5,E6,E7,F5,
F6,F7,G5,G6,
G7,H2,H5,H6
,H7,J5,J6,J7,
K5,K6,K7,L5,
L6,L7,M5,M6,
M7,N4,N8
–
Power Supply
Power supply inputs to the core of the device.
V
SS
Ground
Ground for the core of the device.
V
SSQ
V
DDQ
5,10,21,26,
55,60,71,76
–
I/O Ground
Ground for the I/O circuitry.
4,11,20,27, A1,F1,J1, C3,C9,D3,D9, I/O Power Sup-
Power supply for the I/O circuitry.
54,61,70,77 M1,U1,A7, E3,E9,F3,F9,
ply
F7,J7,M7, G3,G9,J3,J9,
U7
K3,K9,L3,L9,
M3,M9,N3,N9
31
R3
R1
Input-
Static
Selects Burst Order.
When tied to GND selects linear
burst sequence. When tied to V
DD
or left floating selects
interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin
has an internal pull-up.
Serial data-out to the JTAG circuit.
Delivers data on
the negative edge of TCK. If the JTAG feature is not
being utilized, this pin should be disconnected. This pin
is not available on TQFP packages.
Serial data-In to the JTAG circuit.
Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected to
V
DD
. This pin is not available on TQFP packages.
Serial data-In to the JTAG circuit.
Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected to
V
DD
. This pin is not available on TQFP packages.
MODE
TDO
–
U5
P7
JTAG serial
output
Synchronous
JTAG serial
input
Synchronous
JTAG serial
input
Synchronous
TDI
–
U3
P5
TMS
–
U2
R5
Document #: 38-05096 Rev. *B
Page 7 of 32
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