CY7C1366B
CY7C1367B
CY7C1367B–Pin Definitions
(continued)
Name
ADV
TQFP
83
BGA
(2-Chip
Enable)
G4
fBGA
A9
I/O
Input-
Synchronous
Input-
Synchronous
Description
Advance Input signal, sampled on the rising edge of
CLK, active LOW.
When asserted, it automatically
increments the address in a burst cycle.
Address Strobe from Processor, sampled on the
rising edge of CLK, active LOW.
When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE
1
is
deasserted HIGH.
Address Strobe from Controller, sampled on the
rising edge of CLK, active LOW.
When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
ADSP
84
A4
B9
ADSC
85
P4
A8
Input-
Synchronous
ZZ
64
T7
H11
Input-
ZZ “sleep” Input, active HIGH.
When asserted HIGH
Asynchronous places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal
pull-down.
I/O-
Synchronous
Bidirectional Data I/O lines.
As inputs, they feed into
an on-chip data register that is triggered by the rising
edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses
presented during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP
X
are placed in a three-state
condition.
DQs, DQPs 58,59,62,63,
68,69,72,73,
8,9,12,13,18
,19,22,23,74
,24
P7,K7,G7, J10,K10,L10,
E7,F6,H6,
M10,D11,
L6,N6,D1, E11,F11,G11
H1,L1,N1, ,J1,K1,L1,M1
E2,G2,K2, ,D2,E2,F2,
M2,D6,P2 G2,C11,N1
V
DD
15,41,65,91
C4,J2,J4, D4,D8,E4,E8 Power Supply
Power supply inputs to the core of the device.
J6,R4
,F4,F8,G4,
G8,H4,H8,J4
,J8,K4,K8,L4
,L8,M4,M8
H2,C4,C5,C6
,C7,C8,D5,
D6,D7,E5,E6
,E7,F5,F6,F7
,G5,G6,G7,
H5,H6,H7,J5
,J6,J7,K5,K6,
K7,L5,L6,L7,
M5,M6,M7,
N4,N8
–
Ground
Ground for the core of the device.
V
SS
17,40,67,90 D3,D5,E5,
E3,F3,F5,
G5,H3,H5,
K3,K5,L3,
M3,M5,N3,
N5,P3,P5
V
SSQ
5,10,21,26,
55,60,71,76
–
I/O Ground
Ground for the I/O circuitry.
Document #: 38-05096 Rev. *B
Page 9 of 32
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