CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms
Write Cycle Timing
t
CLK
t
CLKH
WCLK
t
DS
D
0
–D
17
t
ENS
WEN
t
WFF
FF
t
SKEW1 [14]
RCLK
t
WFF
t
ENH
NO OPERATION
t
CLKL
t
DH
REN
4275V–8
Read Cycle Timing
t
CLK
t
CLKH
RCLK
t
ENS
REN
t
REF
EF
t
A
Q
0
–Q
17
t
OLZ
t
OE
OE
t
SKEW2
[15]
WCLK
VALID DATA
t
CLKL
t
ENH
NO OPERATION
t
REF
t
OHZ
WEN
4275V–9
Notes:
14. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then FF may not change state until the next WCLK rising edge.
15. t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
, then EF may not change state until the next RCLK rising edge.
Document #: 38-06012 Rev. *A
Page 7 of 20
CYPRESS [ CYPRESS SEMICONDUCTOR ]
