CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms
(continued)
Reset Timing
[16]
t
RS
RS
t
RSR
REN, WEN,
LD
t
RSF
EF,PAE
t
RSF
FF,PAF,
HF
t
RSF
Q
0 –
Q
17
OE=0
4275V–10
OE=1
[17]
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D
0
–D
17
t
ENS
WEN
t
SKEW2
RCLK
t
REF
EF
t
FRL
[18]
D
0
(FIRSTVALID WRITE)
D
1
D
2
D
3
D
4
REN
t
A
Q
0
–Q
17
t
OLZ
t
OE
OE
4275V–11
t
A
D
0
[19]
D
1
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
18. When t
SKEW2
> minimum specification, t
FRL
(maximum) = t
CLK
+ t
SKEW2
. When t
SKEW2
< minimum specification, t
FRL
(maximum) = either 2*t
CLK
+ t
SKEW2
or t
CLK
+ t
SKEW2
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
19. The first word is always available the cycle after EF goes HIGH.
Document #: 38-06012 Rev. *A
Page 8 of 20
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