CYP15G0401DXB
CYV15G0401DXB
CYW15G0401DXB
Transmit Path Block Diagram
REFCLK+
REFCLK–
TXRATE
SPDSEL
TXCLKO+
TXCLKO–
TXMODE[1:0]
TXCKSEL
TXPERA
SCSEL
Input
Register
TXDA[7:0]
TXOPA
TXCTA[1:0]
8
2
12
2
Character-Rate Clock
Transmit
Mode
BIST Enable
Latch
4
Output
Enable
Latch
8
Phase-align
Buffer
Shifter
Parity
Check
12
12
BIST LFSR
8B/10B
10
OUTA1+
OUTA1–
OUTA2+
OUTA2–
TXLBA
Character-Rate Clock
Transmit PLL
Clock Multiplier
Bit-rate Clock
BISTLE
BOE[7:0]
RBIST[D:A]
OELE
= Internal Signal
H M L
TXCLKA
TXPERB
Phase-align
Buffer
BIST LFSR
8B/10B
Input
Register
Shifter
Parity
Check
TXDB[7:0]
TXOPB
TXCTB[1:0]
8
2
11
11
12
10
OUTB1+
OUTB1–
OUTB2+
OUTB2–
TXLBB
H M L
TXCLKB
TXPERC
Phase-align
Buffer
Input
Register
Shifter
Parity
Check
TXDC[7:0]
TXOPC
TXCTC[1:0]
8
2
11
11
12
BIST LFSR
8B/10B
10
OUTC1+
OUTC1–
OUTC2+
OUTC2–
TXLBC
H M L
TXCLKC
TXPERD
Phase-align
Buffer
BIST LFSR
8B/10B
Input
Register
Shifter
Parity
Check
TXDD[7:0]
TXOPD
TXCTD[1:0]
8
11
11
12
10
OUTD1+
OUTD1–
OUTD2+
OUTD2–
TXLBD
H M L
TXCLKD
TXRST
PARCTL
Document #: 38-02002 Rev. *L
Parity Control
Page 4 of 53
CYPRESS [ CYPRESS SEMICONDUCTOR ]
