CYP15G0401DXB
CYV15G0401DXB
CYW15G0401DXB
Receive Path Block Diagram
RXLE
BOE[7:0]
RX PLL Enable
Latch
= Internal Signal
TRSTZ
JTAG
Boundary
Scan
Controller
TMS
TCLK
TDI
TDO
LFIA
Elasticity
Buffer
10B/8B
BIST
Framer
Output
Register
Shifter
8
3
RXDA[7:0]
RXOPA
RXSTA[2:0]
RXCLKA+
RXCLKA–
LFIB
Framer
Elasticity
Buffer
10B/8B
BIST
Shifter
Output
Register
8
3
RXDB[7:0]
RXOPB
RXSTB[2:0]
RXCLKB+
RXCLKB–
LFIC
Elasticity
Buffer
10B/8B
BIST
Framer
Output
Register
Shifter
8
3
RXDC[7:0]
RXOPC
RXSTC[2:0]
RXCLKC+
RXCLKC–
LFID
Elasticity
Buffer
10B/8B
BIST
Output
Register
Framer
Shifter
8
3
RXDD[7:0]
RXOPD
RXSTD[2:0]
RXCLKD+
RXCLKD–
2
Bonding
Control
Parity Control
Character-Rate Clock
SDASEL
LPEN
INSELA
INA1+
INA1–
INA2+
INA2–
TXLBA
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Clock
Select
÷2
INSELB
INB1+
INB1–
INB2+
INB2–
TXLBB
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Clock
Select
÷2
INSELC
INC1+
INC1–
INC2+
INC2–
TXLBC
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Clock
Select
÷2
INSELD
IND1+
IND1–
IND2+
IND2–
TXLBD
RBIST[D:A]
FRAMCHAR
RXRATE
RFEN
RFMODE
RXCKSEL
DECMODE
RXMODE[1:0]
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Clock
Select
÷2
2
BONDST
BOND_ALL
BOND_INH
MASTER
Page 5 of 53
Document #: 38-02002 Rev. *L
CYPRESS [ CYPRESS SEMICONDUCTOR ]
