FAN5078 DDR/ACPI Regulator Combo
Block Diagrams
R4
+5VSB
+12V
+5MAIN
S3#O
Q4
C13
Q7
+5VSB
SBSW
Q6
+5MAIN
S3#O
3
1
16
18
17
15
13
9
10
C3
SS
VCC
21
14
11
HDRV
SW
ISNS
R3
Q2
LDRV
GND
FB
C9
COMP
VDDQ IN
REF IN
VTT SNS
VTT OUT
C7
C8
R10
Q3
5V USB
C14
C15
SBUSB#
3.3 MAIN
Q5
4
5V MAIN
S4ST#
BOOT
Q1
C5
C2
5V DUAL
L2
S3#O
EN
S3#I
3.3 ALW
PGOOD
ACPI
CONTROL
&
LOGIC
2
8
C
IN
C12
L1
VDDQ
C
OUT
+5VSB
PWM
C4
R5
ILIM
12
P1
23
22
7
R2
R1
R6
C6
R9
20
VTT
LDO
24
5
6
Figure 1. Typical DDR/ACPI System Regulation Schematic
Components are selected for a 15A VDDQ output.
© 2006 Fairchild Semiconductor Corporation
FAN5078 Rev. 1.0.0 • 05/11/06
2
www.fairchildsemi.com