FAN5078 DDR/ACPI Regulator Combo
5VSB
VCC
D2
BOOT
C
BOOT
VIN
Q1
S3#I
S3
HDRV
OVP
FB
RAMP
CLK
COMP
FB
S
Q
R
RAMP
S/H
SW
Q2
VDD
LDRV
PGND
L
OUT
VDDQ
C
OUT
EN
POR/UVLO
ADAPTIVE
GATE
CONTROL LOGIC
PWM
OSC
PWM
4.41K
ILIM det.
ISNS
SS
PGOOD
VDDQ IN
ISNS
R
SENSE
CURRENT PROCESSING
Reference and
Soft Start
VREF
ILIM
R
ILIM
VDDQ
Figure 2. PWM Modulator Block Diagram
VDDQ IN
R9
S3#I
50K
REF IN
R10
VDDQ IN
+
50K
EN
VTT OUT
–
110K
VTT SNS
PGND
Figure 3. VTT Regulator Block Diagram
© 2006 Fairchild Semiconductor Corporation
FAN5078 Rev. 1.0.0 • 05/11/06
4
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