FMP1617CA0(7)
CMOS LPRAM
1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM
FEATURES
• Process Technology : Full CMOS
• Three state output and TTL Compatible
• Organization : 1M x 16
2
• Package Type : 48-FBGA-6.00x8.00 mm
• Power Supply Voltage : 2.7~3.3V
FMP1617CA0(7)-FxxX : Normal
• Dual CS & Page Modes
FMP1617CA0 : Dual CS
FMP1617CA0(7)-GxxX : Pb-Free
FMP1617CA0(7)-HxxX : Pb-Free & Halogen Free
FMP1617CA7 : Page mode with Dual CS
• Operating Temperature Ranges:
• Separated I/O power(VCCQ) & Core Power(VCC)
• Easy memory expansion with /CS1, CS2, and /OE features
• Automatic power-down when deselected
Special (-10’C to +60’C)
Commercial (0’C to +70’C)
Extended (-25’C to +85’C)
Industrial (-40’C to +85’C)
PRODUCT FAMILY
Power Dissipation
Operating
Voltage (V)
ISB1
ICC1
ICC2
Speed
Product Family
(CMOS Standby
Current)
f = 1MHz
f = fmax
Min. Typ. Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
FMP1617CA0(7)-G60E
2.7 3.0 3.3
60ns
70ns
15mA
12mA
1.5mA
3mA
20mA
70uA
100uA
FMP1617CA0(7)-G70E
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C.
2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER
3. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C)
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Precharge circuit.
Clk gen.
CS2
I/O1
/LB
/OE
/UB
A0
A3
A1
A4
A2
A
B
I/O9
/CS1
VCC
VSS
I/O10
VSS
I/O11
I/O12
A6
A7
I/O2
I/O4
I/O5
I/O6
I/O3
VCC
VSS
I/O7
I/O8
NC
A5
C
D
E
F
Memory array
Row
Addresses
Row
select
A17
A16
A15
A13
A10
VCCQ
I/O15
I/O16
A18
I/O13 DNU
I/O14 A14
I/O Circuit
Data
cont
I/O1~I/O8
A19
A8
A12
A9
WE
A11
Column select
G
H
Data
cont
I/O9~I/O16
Data
cont
48-FBGA : Top View(Ball Down)
Column Addresses
Name
CS2
Function
Name
VCC
VCCQ
VSS
/UB
Function
Core Power
Chip Select Input
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
/CS1
/OE
I/O Power
/CS1
CS2
/OE
/WE
/UB
/LB
Ground
Control Logic
/WE
Upper Byte(I/O9~16)
Lower Byte(I/O 1~8)
Do Not Use
A0~A19
/LB
I/O1~I/O16 Data Inputs/Outputs
DNU
Revision 0.1
Jun. 2006
2
FIDELIX [ FIDELIX ]
