FMP1617CA0(7)
CMOS LPRAM
WRITE CYCLE (1) (/WE controlled)
tWC
Address
tCW(2)
tWR(4)
/CS1
CS2
tAW
tBW
/UB, /LB
/WE
tWP(1)
tAS(3)
High-Z
tDW
Data Valid
tDH
Data in
High-Z
tWHZ
tOW
Data Out
Data Undefined
WRITE CYCLE (2) (/CS1 controlled)
tWC
Address
tWR(4)
tAS(3)
tCW(2)
/CS1
CS2
tAW
tBW
/UB, /LB
/WE
tWP(1)
tDW
Data Valid
tDH
Data in
Data Out
High-Z
High-Z
WRITE CYCLE (3) (CS2 controlled)
tWC
Address
tWR(4)
tCW(2)
/CS1
tAS(3)
CS2
tAW
tBW
/UB, /LB
tWP(1)
/WE
tDW
Data Valid
tDH
Data in
Data Out
High-Z
High-Z
Revision 0.1
Jun. 2006
8