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FMP1617CA7-HXXX 参数 Datasheet PDF下载

FMP1617CA7-HXXX图片预览
型号: FMP1617CA7-HXXX
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×16位超低功耗和低电压全CMOS RAM [1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM]
分类和应用:
文件页数/大小: 10 页 / 208 K
品牌: FIDELIX [ FIDELIX ]
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FMP1617CA0(7)  
CMOS LPRAM  
WRITE CYCLE (4) (/UB, /LB controlled)  
tWC  
Address  
tWR(4)  
tCW(2)  
/CS1  
CS2  
tAW  
tBW  
/UB, /LB  
/WE  
tAS(3)  
tWP(1)  
tDW  
Data Valid  
tDH  
Data in  
Data Out  
High-Z  
High-Z  
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with  
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write  
ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to  
the end of write.  
2. tCW is measured from the /CS going low to end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.  
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.  
PAGE WRITE CYCLE (Address controlled, CS2=VIH)  
tMRC  
tPC  
tPC  
tPC  
tPC  
tPC  
tPC  
tPC  
tWC  
A0~A3  
A4~A20  
/CS1  
CS2  
/UB, /LB  
tAS(3)  
/WE  
tDH  
Data Valid  
tOW  
tDH tDW  
tDH tDW tDH  
tDH  
Data Valid Data Valid Data Valid  
tDW  
tDW  
tDW tDH  
tDH  
tDH tDW  
tDW  
tDW  
Data in  
Data Out  
High-Z  
High-Z  
Data Valid  
Data Valid  
Data Valid  
Data Valid  
tWHZ  
Data Undefined  
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with  
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write  
ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to  
the end of write.  
2. tCW is measured from the /CS going low to end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.  
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.  
6. In case page address is over 3ns, write to the invalid address can occur.  
Revision 0.1  
Jun. 2006  
9