Layout Practices
Table 7. Mandatory Reset Configuration of MPC875/870 (continued)
Register/Configuration
PCDIR
(Port C data direction register)
PDPAR
(Port D pin assignment register)
PDDIR
(Port D data direction register)
Field
PCDIR[4:5]
PCDIR[8:9]
PCDIR[14]
PDPAR[3:7]
PDPAR[9:5]
PDDIR[3:7]
PDDIR[9:15]
Value
(binary)
0
0
0
10 Layout Practices
Each V
DD
pin on the MPC875/870 should be provided with a low-impedance path to the board’s supply. Each GND
pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups
of logic on chip. The V
DD
power supply should be bypassed to ground using at least four 0.1-µF bypass capacitors
located as close as possible to the four sides of the package. Each board designed should be characterized and
additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed
circuit traces connecting to chip V
DD
and GND should be kept to less than half an inch per capacitor lead. At a
minimum, a four-layer board employing two inner layers as V
DD
and GND planes should be used.
All output pins on the MPC875/870 have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reflections caused by these fast output switching times.
This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches
are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to
the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads because these loads create higher transient currents in the V
DD
and GND circuits. Pull up all unused
inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins. For more information, please refer to Section 14.4.3, “Clock Synthesizer Power (V
DDSYN
,
V
SSSYN
, V
SSSYN1
),” of the
MPC885 PowerQUICC Family User’s Manual.
11 Bus Signal Timing
The maximum bus speed supported by the MPC875/870 is 80 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC875/870 used at 133 MHz must be configured for a 66 MHz bus).
shows the frequency ranges for standard part frequencies in 1:1 bus mode, and Table 9 shows the frequency ranges
for standard part frequencies in 2:1 bus mode.
Table 8. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part Frequency
66 MHz
Min
Core frequency
Bus frequency
40
40
Max
66.67
66.67
80 MHz
Min
40
40
Max
80
80
MPC875/MPC870 Hardware Specifications, Rev. 3.0
15
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
