MC9S12P64CFT 参数 Datasheet PDF下载

Device Overview MC9S12P-Family

Table 1-12. Interrupt Vector Locations (Sheet 3 of 3)

Vector Address

(1)

Vector base + $AE

to

Vector base + $90

Vector base + $8E

Vector base+ $8C

Vector base + $8A

Vector base + $88

Vector base + $86

Vector base + $84

Vector base + $82

Vector base + $80

1. 16 bits vector address based

Spurious interrupt

—

Port P interrupt

PWM emergency shutdown

Low-voltage interrupt (LVI)

Autonomous periodical interrupt

(API)

High temperature interrupt

ATD compare interrupt

I bit

I bit

I bit

I bit

I bit

I bit

Interrupt Source

CCR

Mask

Local Enable

Wake up

Wakeup

from STOP from WAIT

Reserved

PIEP (PIEP7,PIEP5-PIEP0)

PWMSDN (PWMIE)

CPMUCTRL (LVIE)

CPMUAPICTRL (APIE)

CPMUHTCL (HTIE)

ATDCTL2 (ACMPIE)

Reserved

None

-

-

Yes

No

No

Yes

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

1.11.3

Effects of Reset

When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections

for register reset states.

On each reset, the Flash module executes a reset sequence to load Flash configuration registers.

1.11.3.1

Flash Configuration Reset Sequence Phase

On each reset, the Flash module will hold CPU activity while loading Flash module registers from the

Flash memory. If double faults are detected in the reset phase, Flash module protection and security may

be active on leaving reset. This is explained in more detail in the Flash module section

13.6 Initialization.

1.11.3.2

Reset While Flash Command Active

If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The

state of the word being programmed or the sector/block being erased is not guaranteed.

1.11.3.3

I/O Pins

Refer to the PIM section for reset configurations of all peripheral module ports.

1.11.3.4

Memory

The RAM arrays are not initialized out of reset.

S12P-Family Reference Manual, Rev. 1.13

46

Freescale Semiconductor