Device Overview MC9S12P-Family
1.12
COP Configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are
loaded from the Flash register FOPT. See
Table 1-13
and
Table 1-14
for coding. The FOPT register is
loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence.
Table 1-13. Initial COP Rate Configuration
NV[2:0] in
FOPT Register
000
001
010
011
100
101
110
111
CR[2:0] in
COPCTL Register
111
110
101
100
011
010
001
000
Table 1-14. Initial WCOP Configuration
NV[3] in
FOPT Register
1
0
WCOP in
COPCTL Register
0
1
1.13
ATD External Trigger Input Connection
The ATD module includes external trigger inputs ETRIG0 and ETRIG1. The external trigger allows the
user to synchronize ATD conversion to external trigger events.
Table 1-15
shows the connection of the
external trigger inputs.
Table 1-15. ATD External Trigger Sources
External Trigger
Input
ETRIG0
ETRIG1
Connectivity
PWM channel 1
PWM channel 3
Consult the ATD section for information about the analog-to-digital converter module. References to
freeze mode are equivalent to active BDM mode.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
47
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
