MC9S12P64CFT 参数 Datasheet PDF下载

Device Overview MC9S12P-Family

1.9.2

Low Power Operation

The MC9S12P has two static low-power modes Pseudo Stop and Stop Mode. For a detailed description

refer to S12CPMU section.

1.10

Security

The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to

Section 5.4.1

Security

and

Section 13.5 Security

1.11

Resets and Interrupts

Consult the S12 CPU manual and the S12SINT section for information on exception processing.

1.11.1

Resets

Table 1-11. lists all Reset sources and the vector locations. Resets are explained in detail in the

Section

Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU)

Table 1-11. Reset Sources and Vector Locations

Vector Address

$FFFE

$FFFE

$FFFE

$FFFE

$FFFC

$FFFA

Reset Source

Power-On Reset (POR)

Low Voltage Reset (LVR)

External pin RESET

Illegal Address Reset

Clock monitor reset

COP watchdog reset

CCR

Mask

None

None

None

None

None

None

Local Enable

None

None

None

None

OSCE Bit in CPMUOSC register

CR[2:0] in CPMUCOP register

1.11.2

Interrupt Vectors

Table 1-12

lists all interrupt sources and vectors in the default order of priority. The interrupt module (see

Section Chapter 4 Interrupt Module (S12SINTV1))

provides an interrupt vector base register (IVBR)

Vector Address

(1)

Vector base + $F8

Vector base+ $F6

Vector base+ $F4

Vector base+ $F2

Interrupt Source

Unimplemented instruction trap

SWI

XIRQ

IRQ

CCR

Mask

None

None

X Bit

I bit

Local Enable

None

None

None

IRQCR (IRQEN)

Wake up

Wakeup

from STOP from WAIT

-

-

Yes

Yes

-

-

Yes

Yes

S12P-Family Reference Manual, Rev. 1.13

44

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