General
Table 9. Device clock specifications (continued)
Symbol
f
LPTMR_pin
f
LPTMR_ERCLK
f
I2S_MCLK
f
I2S_BCLK
Description
LPTMR clock
LPTMR external reference clock
I2S master clock
I2S bit clock
Min.
—
—
—
—
Max.
25
16
12.5
4
Unit
MHz
MHz
MHz
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, and I
2
C signals.
Table 10. General switching specifications
Symbol
Description
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ V
DD
≤ 2.7V
• 2.7 ≤ V
DD
≤ 3.6V
• Slew enabled
• 1.71 ≤ V
DD
≤ 2.7V
• 2.7 ≤ V
DD
≤ 3.6V
—
—
36
24
Table continues on the next page...
—
—
7
ns
ns
13
ns
ns
Min.
1.5
100
50
100
2
Max.
—
—
—
—
—
Unit
Bus clock
cycles
ns
ns
ns
Bus clock
cycles
Notes
K10 Sub-Family Data Sheet, Rev. 4 5/2012.
20
Freescale Semiconductor, Inc.
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
