Peripheral operating requirements and behaviors
6.1.1 JTAG electricals
Table 12. JTAG voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
TCLK frequency of operation
• JTAG
2.7
5.5
J1
MHz
—
—
10
5
• CJTAG
J2
J3
TCLK cycle period
TCLK clock pulse width
• JTAG
1/J1
—
ns
100
200
—
—
ns
ns
ns
ns
ns
• CJTAG
J4
J5
TCLK rise and fall times
—
1
TMS input data setup time to TCLK rise
53
112
8
—
—
—
• JTAG
• CJTAG
J6
J7
TDI input data setup time to TCLK rise
ns
ns
TMS input data hold time after TCLK rise
3.4
3.4
3.4
—
—
—
• JTAG
• CJTAG
J8
J9
TDI input data hold time after TCLK rise
ns
ns
TCLK low to TMS data valid
• JTAG
—
—
—
—
48
85
48
3
• CJTAG
J10
J11
TCLK low to TDO data valid
ns
ns
Output data hold/invalid time after clock edge1
1. They are common for JTAG and CJTAG. Input transition = 1 ns and Output load = 50pf
J2
J3
J3
TCLK (input)
J4
J4
Figure 4. Test clock input timing
K10 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
23
FREESCALE [ Freescale ]
