Peripheral operating requirements and behaviors
Table 31. Slave mode DSPI timing (limited voltage range) (continued)
Num
DS9
DS10
DS11
DS12
DS13
DS14
DS15
DS16
Description
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Min.
4 x t
BUS
(t
SCK
/2) − 2
—
0
2
7
—
—
Max.
—
(t
SCK
/2) + 2
20
—
—
—
14
14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DS13
DS15
DS12
First data
DS14
First data
Data
Last data
DS11
Data
Last data
DS16
DSPI_SIN
Figure 16. DSPI classic SPI timing — slave mode
6.8.2 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 32. Master mode DSPI timing (full voltage range)
Num
Operating voltage
Frequency of operation
DS1
DS2
DSPI_SCK output cycle time
DSPI_SCK output high/low time
Description
Min.
1.71
—
4 x t
BUS
(t
SCK
/2) - 4
Max.
3.6
12.5
—
(t
SCK/2)
+ 4
Unit
V
MHz
ns
ns
Notes
Table continues on the next page...
K10 Sub-Family Data Sheet, Rev. 4 5/2012.
46
Freescale Semiconductor, Inc.
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
