Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DS13
DS15
DS12
First data
DS14
First data
Data
Last data
DS11
Data
Last data
DS16
DSPI_SIN
Figure 18. DSPI classic SPI timing — slave mode
6.8.3 I
2
C switching specifications
See
General switching specifications.
6.8.4 UART switching specifications
See
General switching specifications.
6.8.5 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
K10 Sub-Family Data Sheet, Rev. 4 5/2012.
48
Freescale Semiconductor, Inc.
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
