Peripheral operating requirements and behaviors
Table 21. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
tDHS
Propagation delay, high-speed mode (EN = 1, PMODE
= 1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN = 1, PMODE
= 0)
80
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
40
—
μs
μA
LSB3
IDAC6b
INL
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
CMPHysteresisvsVinn
90.00E-03
80.00E-03
70.00E-03
60.00E-03
HYSTCTR
Setting
50.00E-03
0
1
40.00E-03
2
3
30.00E-03
20.00E-03
10.00E-03
000.00E+00
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinn (V)
Figure 7. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
CMPHysteresisvsVinn
180.00E-03
160.00E-03
140.00E-03
120.00E-03
HYSTCTR
Setting
100.00E-03
0
1
2
3
80.00E-03
60.00E-03
40.00E-03
20.00E-03
000.00E+00
-20.00E-03
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinn (V)
Figure 8. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
34
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
