Peripheral operating requirements and behaviors
6.8.3 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's Reference Manual for information about the modified transfer formats used for
communicating with slower peripheral devices.
All timing is shown with respect to 20% V
DD
and 80% V
DD
thresholds, unless noted, as
well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 23. SPI master mode timing on slew rate disabled pads
Num.
1
2
3
4
5
6
7
8
9
10
11
Symbol
f
op
t
SPSCK
t
Lead
t
Lag
t
WSPSCK
t
SU
t
HI
t
v
t
HO
t
RI
t
FI
t
RO
t
FO
Description
Frequency of operation
SPSCK period
Enable lead time
Enable lag time
Clock (SPSCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
Fall time input
Rise time output
Fall time output
—
25
ns
—
Min.
f
periph
/2048
2 x t
periph
1/2
1/2
t
periph
- 30
16
0
—
0
—
Max.
f
periph
/2
2048 x
t
periph
—
—
1024 x
t
periph
—
—
10
—
t
periph
- 25
Unit
Hz
ns
t
SPSCK
t
SPSCK
ns
ns
ns
ns
ns
ns
Note
—
—
—
—
—
—
—
—
1. For SPI0 f
periph
is the bus clock (f
BUS
). For SPI1 f
periph
is the system clock (f
SYS
).
2. t
periph
= 1/f
periph
Table 24. SPI master mode timing on slew rate enabled pads
Num.
1
2
3
4
5
6
Symbol
f
op
t
SPSCK
t
Lead
t
Lag
t
WSPSCK
t
SU
Description
Frequency of operation
SPSCK period
Enable lead time
Enable lag time
Clock (SPSCK) high or low time
Data setup time (inputs)
Table continues on the next page...
Min.
f
periph
/2048
2 x t
periph
1/2
1/2
t
periph
- 30
96
Max.
f
periph
/2
2048 x
t
periph
—
—
1024 x
t
periph
—
Unit
Hz
ns
t
SPSCK
t
SPSCK
ns
ns
Note
—
—
—
—
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
36
Freescale Semiconductor, Inc.
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
