AC Electrical Characteristics
NOTE
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing.
This figure shows the interaction of several bus signals.
CLKin
sp11
AACK/TA/TS/
DBG/BG/BR input signals
sp11a
ARTRY/TEA input signals
sp12
DATA bus normal mode
input signal
sp15
All other input signals
sp31
PSDVAL/TEA/TA output signals
sp32
ADD/ADD_atr/BADDR/CI/
GBL/WT output signals
sp33
DATA bus output signals
sp30
sp30
sp10
sp10
sp10
sp10
sp30
sp35
sp30
All other output signals
(except AP)
sp13
DATA bus pipeline mode
input signal
sp10
Figure 9. Bus Signals
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
24
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
