AC Electrical Characteristics
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
6.3
JTAG Timings
Table 15. JTAG Timings
1
Parameter
Symbol
2
f
JTG
t
JTG
t
JTKHKL
t
JTGR
and
t
JTGF
t
TRST
Boundary-scan data
TMS, TDI
t
JTDVKH
t
JTIVKH
t
JTDXKH
t
JTIXKH
t
JTKLDV
t
JTKLOV
t
JTKLDX
t
JTKLOX
t
JTKLDZ
t
JTKLOZ
Min
0
30
15
0
25
4
4
10
10
—
—
1
1
1
1
Max
33.3
—
—
5
—
—
—
—
—
10
10
—
—
10
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
—
—
—
6
This table lists the JTAG timings.
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4V
JTAG external clock rise and fall times
TRST assert time
Input setup times
3 6
,
4
,
7
4 7
,
4
,
7
4 7
,
5
,
7
5 7
.
5 7
Input hold times
Boundary-scan data
TMS, TDI
Output valid times
Boundary-scan data
TDO
Output hold times
Boundary-scan data
TDO
JTAG external clock to output high impedance
Boundary-scan data
TDO
1
,
5 7
,
5
,
6
5 6
,
2
3
4
5
6
7
All outputs are measured from the midpoint voltage of the falling/rising edge of t
TCLK
to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
JTDVKH
symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
JTG
clock reference
(K) going to the high (H) state or setup time. Also, t
JTDXKH
symbolizes JTAG timing (JT) with respect to the time data input
signals (D) went invalid (X) relative to the t
JTG
clock reference (K) going to the high (H) state. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
Non-JTAG signal input timing with respect to t
TCLK
.
Non-JTAG signal output timing with respect to t
TCLK
.
Guaranteed by design.
Guaranteed by design and device characterization.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
26
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
