System Design Information
R
θ
JC
= junction-to-case thermal resistance (°C/W)
P
D
= power dissipation (W)
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8343EA.
21.1
System Clocking
The MPC8343EA includes two PLLs:
1. The platform PLL generates the platform clock from the externally supplied CLKIN input. The
frequency ratio between the platform and CLKIN is selected using the platform PLL ratio
configuration bits as described in
2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
between the e300 core clock and the platform clock is selected using the e300 PLL ratio
configuration bits as described in
21.2
PLL Power Supply Filtering
Each PLL gets power through independent power supply pins (AV
DD
1, AV
DD
2, respectively). The AV
DD
level should always equal to V
DD
, and preferably these voltages are derived directly from V
DD
through a
low frequency filter scheme.
There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to
provide four independent filter circuits as illustrated in
one to each of the four AV
DD
pins.
Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.
The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built
with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the
recommendations of Dr. Howard Johnson in
High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value
capacitor.
To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the
specific AV
DD
pin being supplied. It should be possible to route directly from the capacitors to the AV
DD
pin, which is on the periphery of package, without the inductance of vias.
shows the PLL power supply filter circuit.
10
Ω
V
DD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
AV
DD
(or L2AV
DD
)
GND
Figure 37. PLL Power Supply Filter Circuit
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
72
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
