Power Characteristics
supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of
time that all input and output pins will actively be driven and cause contention and excessive current from
3A to 5A. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the
core voltage (V
DD
) before the I/O voltage (GV
DD
, LV
DD
, and OV
DD
) and assert PORESET before the
power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply
must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see
Voltage
I/O Voltage (GV
DD
, LV
DD
, OV
DD
)
Core Voltage (V
DD
, AV
DD
)
0.7 V
90%
Time
Figure 4. Power Sequencing Example
I/O voltage supplies (GV
DD
, LV
DD
, and OV
DD
) do not have any ordering requirements with respect to one
another.
3
Power Characteristics
Table 4. MPC8347EA Power Dissipation
1
Core
Frequency
(MHz)
PBGA
266
CSB
Frequency
(MHz)
266
133
400
266
133
400
200
100
Typical at T
J
= 65
1.3
1.1
1.5
1.4
1.5
1.3
Typical
2
,
3
1.6
1.4
1.9
1.7
1.8
1.7
Maximum
4
1.8
1.6
2.1
1.9
2.0
1.9
Unit
W
W
W
W
W
W
The estimated typical power dissipation for the MPC8347EA device is shown in
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
10
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
